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| preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. july 2010 doc id 17659 rev 1 1/106 1 stm32l151xx stm32l152xx ultralow power arm-based 32-bit mcu with up to 128 kb flash, rtc, lcd, usb, usart, i2c, spi, timers, adc, dac, comparators features operating conditions ? operating power supply range: 1.65 v to 3.6 v (without bor) or 1.8 v to 3.6 v (with bor option) ? temperature range: ?40 to 85 c low power features ? 4 modes: sleep, low-power run (15 a at 32 khz), low-power sleep (4 a), stop with rtc (1.2 a), stop (0.5 a), standby (0.27 a) ? dynamic core voltage scaling down to 233 a/mhz ? ultralow leakage per i/o: 50 na ? fast wakeup from stop: 8 s ? three wakeup pins core: arm 32-bit cortex ? -m3 cpu ? 32 mhz maximum frequency, 33.3 dmips peak (dhrystone 2.1) ? memory protection unit reset and supply management ? low power, ultrasafe bor (brownout reset) with 5 selectable thresholds ? ultralow power por/pdr ? programmable voltage detector (pvd) clock management ? 1 to 24 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 16 mhz factory-trimmed rc ? internal 37 khz low consumption rc ? internal multispeed low power rc, 64 khz to 4 mhz with a consumption down to 1.5 a ? pll for cpu clock and usb (48 mhz) low power calendar rtc ? alarm, periodic wakeup from stop/standby memories ? up to 128 kbyte of flash memory with ecc ? 4 kbyte of data eeprom with ecc ? up to 16 kbyte of ram up to 83 fast i/os (73 of which are 5 v-tolerant) all mappable on 16 external interrupt vectors development support ? serial wire debug, jtag and trace dma: 7-channel dma c ontroller, supporting timers, adc, spis, i 2 cs and usarts lcd 8 40 or 4 44 with step-up converter 12-bit adc up to 1 msps/24 channels ? temperature sensor and internal voltage reference ? operates down to 1.8 v 2 12-bit dacs with output buffers 2 ultralow power comparators ? window mode and wakeup capability 10 timers: ? 6 16-bit general-purpose timers, each with up to 4 ic/oc/pwm channels ? 2 16-bit basic timers ? 2 watchdog timers (independent and window) up to 8 communication interfaces ? up to 2 i 2 c interfaces (smbus/pmbus) ? up to 3 usarts (iso 7816 interface, lin, irda capabilit y, modem control) ? up to 2 spis (16 mbit/s) ? usb 2.0 full-speed interface crc calculation unit, 96-bit unique id table 1. device summary reference part number stm32l151xx stm32l151cb, stm32l151rb, stm32l151vb, stm32l151c8, stm32l151r8, stm32l151v8 stm32l152xx stm32l152cb, stm32l152rb, stm32l152vb, stm32l152c8, stm32l152r8, stm32l152v8 lqfp100 14 14 mm lqfp64 10 10 mm lqfp48 7 7 mm bga100 7 7 mm bga64 5 5 mm vfqfpn48 7 7 mm www.st.com
contents stm32l151xx, stm32l152xx 2/106 doc id 17659 rev 1 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 ultralow power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.3 common system strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 arm? cortex?-m3 core with mpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.4 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 low power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 17 3.6 gpios (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 dma (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9 lcd (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.10 adc (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11 dac (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 ultralow power comparators and reference voltage . . . . . . . . . . . . . . . . . 21 3.13 routing interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.1 general-purpose timers (tim2, tim3, tim4, tim9, tim10 and tim11) 21 3.14.2 basic timers (tim6 and tim7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.3 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.4 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 stm32l151xx, stm32l152xx contents doc id 17659 rev 1 3/106 3.14.5 window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15.1 i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15.2 universal synchronous/asynchronous receiver transmitter (usart) . . 23 3.15.3 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15.4 universal serial bus (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 23 3.17 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3.2 embedded reset and power control block characteristics . . . . . . . . . . . 46 6.3.3 embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3.5 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.6 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.7 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.8 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.9 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.10 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 70 6.3.11 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.12 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.13 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 contents stm32l151xx, stm32l152xx 4/106 doc id 17659 rev 1 6.3.14 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.15 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.16 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.17 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.18 comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.19 lcd controller (stm32l152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 102 8 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 stm32l151xx, stm32l152xx list of tables doc id 17659 rev 1 5/106 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. ultralow power stm32l15xxx device features and peripheral counts . . . . . . . . . . . . . . . . 10 table 3. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 4. stm32l15xxx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5. alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 6. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 7. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 8. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 9. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 10. functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 45 table 11. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 12. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 table 13. current consumption in run mode, code with data processing running from flash. . . . . . 50 table 14. current consumption in run mode, code wit h data processing running from ram . . . . . . 51 table 15. current consumption in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 16. current consumption in low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 17. current consumption in low power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 18. typical and maximum current consumptions in stop mode . . . . . . . . . . . . . . . . . . . . . . . . 55 table 19. typical and maximum current consumptions in standby mode . . . . . . . . . . . . . . . . . . . . . 56 table 20. typical and maximum timings in low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 21. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 22. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 23. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 24. hse 1-24 mhz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 table 25. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 26. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 27. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 28. msi oscillator ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 29. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 30. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 31. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 32. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 33. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 34. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 35. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 36. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 37. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 38. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 39. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 40. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 41. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 42. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 43. scl frequency (f pclk1 = 36 mhz, v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 44. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 45. usb startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 46. usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 47. usb: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 48. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 list of tables stm32l151xx, stm32l152xx 6/106 doc id 17659 rev 1 table 49. adc accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 50. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 51. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 52. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 53. comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 54. comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 55. lcd controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 56. vfqfpn48 ? very thin fine pitch q uad flat pack nolead 7 7 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 57. tfbga64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 96 table 58. ufbga100 - ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 59. lqpf100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . . 98 table 60. lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . . 99 table 61. lqfp48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 100 table 62. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 63. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 stm32l151xx, stm32l152xx list of figures doc id 17659 rev 1 7/106 list of figures figure 1. ultralow power stm32l15xxx block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3. stm32l15xxx ufbga100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 4. stm32l15xxx tfbga64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 5. stm32l15xxx lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 figure 6. stm32l15xxx lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 7. stm32l15xxx lqfp48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 8. stm32l15xxx vfqfpn48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 9. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 10. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 11. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 12. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 13. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 10. power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 14. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 15. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 16. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 17. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 18. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 19. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 20. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 21. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 22. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 23. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 24. usb timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 25. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 26. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 27. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . . 86 figure 28. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . . 87 figure 29. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 30. vfqfpn48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 31. recommended footprint (dimensions in mm) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 32. recommended pcb design rules for pads (0.5 mm pitch bga) . . . . . . . . . . . . . . . . . . . . 95 figure 33. tfbga64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 96 figure 34. ufbga100 - ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 35. lqfp100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 98 figure 36. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 37. lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 99 figure 38. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 39. lqfp48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 100 figure 40. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 41. lqfp100 p d max vs. t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 introduction stm32l151xx, stm32l152xx 8/106 doc id 17659 rev 1 1 introduction this datasheet provides the ordering information and mechanical device characteristics of the stm32l151xx and stm32l152xx ultralow power arm cortex?-based microcontrollers product line. the ultralow power stm32l15xxx family includes devices in 3 different package types: from 48 pins to 100 pins. depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. these features make the ultralow power stm32l15xxx microcontroller family suitable for a wide range of applications: medical and handheld equipment application control and user interface pc peripherals, gaming, gps and sport equipment alarm systems, wired and wirel ess sensors, video intercom utility metering for information on the cortex?-m3 core please refer to the cortex?-m3 technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337g. figure 1 shows the general block diagram of the device family. stm32l151xx, stm32l152xx description doc id 17659 rev 1 9/106 2 description the ultralow power stm32l15xxx incorporates the connectivity power of the universal serial bus (usb) with the high-performance arm cortex ? -m3 32-bit risc core operating at a 32 mhz frequency, a memory protection un it (mpu), high-speed embedded memories (flash memory up to 128 kbytes and ram up to 16 kbytes), and an extensive range of enhanced i/os and peripherals co nnected to two apb buses. all devices offer a 12-bit adc, 2 dacs and 2 ultralow power comparators, six general-purpose 16-bit timers and two basic timers, which can be used as time bases. moreover, the stm32l15xxx devices contain standard and advanced communication interfaces: up to two i 2 cs and spis, three usarts and a usb. they also include a real-time clock and a set of backup registers that remain powered in standby mode. finally, the integrated lcd controller has a built-in lcd voltage generator that allows you to drive up to 8 multiplexed lcds with contrast independent of the supply voltage. the ultralow power stm32l15 xxx operates from a 1.8 to 3. 6 v power supply (down to 1.65 v at power down) with bor and from a 1.65 to 3.6 v power supply without bor option. it is available in the -40 to +85 c temperature range. a comprehensive set of power-saving modes allows the design of low-power applications description stm32l151xx, stm32l152xx 10/106 doc id 17659 rev 1 2.1 device overview . table 2. ultralow power stm32l15xxx device features and peripheral counts peripheral stm32l15xcx stm32l15xrx stm32l15xvx flash - kbytes 64 128 64 128 64 128 ram - kbytes 10 16 10 16 10 16 timers general-purpose 666 basic 222 communication interfaces spi 222 i 2 c 222 usart 333 usb 111 gpios 37 51 83 12-bit synchronized adc number of channels 1 16 channels 1 20 channels 1 24 channels 12-bit dac number of channels 2 2 2 2 2 2 lcd (stm32l152xx only) com x seg 4x16 4x32 8x28 4x44 8x40 comparator 222 cpu frequency 32 mhz operating voltage 1.8 v to 3.6 v (down to 1.65 v at power-down) with bor option 1.65 v to 3.6 v (down to 1.65 v at power-down) without bor option operating temperatures ambient temperatures: ?40 to +85 c junction temperature: ?40 to + 105 c packages lqfp48, vfqfn48 lqfp64, bga64 lqfp100, bga100 stm32l151xx, stm32l152xx description doc id 17659 rev 1 11/106 2.2 ultralow power device continuum the ultralow power stm32l151xx and stm32l152xx are fully pin-to-pin, software and feature compatible. besides the full compatibilit y within the family, the devices are part of stmicroelectronics microcontrollers ultralow power strategy which also includes stm8l101xx and stm8l15xx devices. th e stm8l and stm32l families allow a continuum of performance, peripherals, system architecture and features. they are all based on stmicroelectronics 0.13 m ultralow leakage process. note: the ultralow power stm32l and genera l-purpose stm32fxxxx families are pin-to-pin compatible. the stm8l15xxx devices are pin-to-pin compatible with the stm8l101xx devices. please refer to the stm32f and stm8l documentation for more information on these devices. 2.2.1 performance all families incorporate highly energy-efficien t cores with both harvar d architecture and pipelined execution: advanced stm8 core fo r stm8l families and arm cortex?-m3 core for stm32l family. in addition specific care for the design architecture has been taken to optimize the ma/dmips and ma/mhz ratios. this allows the ultralow power performance to range from 5 up to 33.3 dmips. 2.2.2 shared peripherals stm8l15xxx and stm32l15xxx share identical peripherals which ensure a very easy migration from one family to another: analog peripherals: adc, dac, and comparators digital peripherals: rtc and some communication interfaces 2.2.3 common system strategy to offer flexibility and optimize performance, the stm8l15xx and st m32l15xx families use a common architecture: same power supply range from 1.65 v to 3.6 v, (1.65 v at power down only for stm8l15xx devices) architecture optimized to reach ultralow consumption both in low power modes and run mode fast startup strategy from low power modes flexible system clock ultrasafe reset: same reset strategy incl uding power-on reset, power-down reset, brownout reset and programmable voltage detector. 2.2.4 features st ultralow power continuum al so lies in feature compatibility: more than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm memory density ranging from 4 to 128 kbytes functional overview stm32l151xx, stm32l152xx 12/106 doc id 17659 rev 1 3 functional overview figure 1 shows the block diagrams. figure 1. ultralow power stm32l15xxx block diagram 1. t a = ?40 c to +105 c (junction temperature up to 125 c). 2. af = alternate function on i/o port pin. % 8 4 ) 4 7 7 $ ' b i t ! $ # * 4 ! ' 3 7 ! & * 4 $ ) * 4 # + 3 7 # + * 4 - 3 3 7 $ . * 4 2 3 4 * 4 $ / . 2 3 4 6 $ $ 6 t o 6 ! & ! ( " 5 3 " $ 0 5 3 " $ - - / 3 ) - ) 3 / 3 # + . 3 3 7 + 5 0 & m a x - ( z 6 3 3 3 # , 3 $ ! 3 - " u s 0 - " u s ) # 6 $ $ 2 % & ? ! $ # ' 0 $ - ! 4 ) - 4 ) - 8 4 ! , / 3 # - ( z 8 4 ! , k ( z / 3 # ? ) . / 3 # ? / 5 4 / 3 # ? / 5 4 / 3 # ? ) . 0 , , ! 0 " & m a x - ( z ! ( " 0 # , + ( # , + c l o c k m a n a g e m e n t ! 0 " 0 # , + a s ! & a s ! & 6 / , 4 2 % ' 6 # / 2 % 0 / 7 % 2 a s ! & 4 ) - " u s - a t r i x ) n t e r f a c e 2 4 # 2 # ( 3 ) b u s $ b u s p b u s o b l & l a s h 5 3 " 2 ! - " 5 3 ! 2 4 5 3 ! 2 4 3 0 ) c h a n n e l s 3 # , 3 $ ! ) # a s ! & 2 8 4 8 # 4 3 2 4 3 5 3 ! 2 4 4 e m p s e n s o r 6 3 3 2 % & ? ! $ # ! ( " & m a x - ( z # h a n n e l s # h a n n e l s # h a n n e l s & # , + ) 7 $ ' 6 $ $ 3 u p p l y m o n i t o r i n g 6 $ $ ! 6 $ $ ! 6 3 3 ! 6 $ $ ! 3 m a r t # a r d a s ! & 2 8 4 8 # 4 3 2 4 3 3 m a r t # a r d a s ! & 2 8 4 8 # 4 3 2 4 3 3 m a r t # a r d a s ! & ! 0 " & m a x - ( z . 6 ) # 3 0 ) - / 3 ) - ) 3 / 3 # + . 3 3 a s ! & ) & 6 $ $ ! 0 6 $ 0 o w e r r e s e t ) n t ! ( " ! 0 " ! 0 " ! 7 5 6 $ $ ! 2 4 # ? ! & 3 y s t e m 0 ! ; = 0 " ; = 0 # ; = 0 $ ; = 0 % ; = , # $ x x 3 % ' x # / - x ) & ) & ) & 6 $ $ ! $ ! # a s ! & $ ! # a s ! & - 0 5 # o m p # / - 0 ? ) . ) . # o m p 4 ) - 4 ) - - 4 ) - 4 ) - 4 ) - # h a n n e l s # h a n n e l # h a n n e l ' e n e r a l p u r p o s e t i m e r s + " & l a s h + " d a t a % % 0 2 / - , # $ s t e p u p c o n v e r t e r 6 , # $ 6 t o 6 6 , # $ " ! 3 ) # 4 ) - % 2 3 3 y n c ( z 6 2 % & / 5 4 0 5 4 a i e # o r t e x - # 0 5 4 r a c e c o n t r o l l e r % 4 - 2 ! - + " b i t $ ! # b i t $ ! # ' 0 ) / ! ' 0 ) / " ' 0 ) / # ' 0 ) / $ ' 0 ) / % 4 2 ! # % # + 4 2 ! # % $ 4 2 ! # % $ 4 2 ! # % $ 4 2 ! # % $ 2 # - 3 2 # , 3 3 t a n d b y i n t e r f a c e " a c k u p i n t e r f a c e 5 3 " & 3 d e v i c e " / 2 6 2 % & ) . 4 0 o w e r u p 0 o w e r d o w n " a c k u p r e g i s t e r 0 ( ; = ' 0 ) / ( stm32l151xx, stm32l152xx functional overview doc id 17659 rev 1 13/106 3.1 low power modes the ultralow power stm32l15xxx supports dyna mic voltage scaling to optimize its power consumption in run mode. the voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system?s maximum operating frequency and the external voltage supply. when executing from flash memory, the consumptions are: in range 1 (v dd range limited to 2.0-3.6 v), with the cpu running at up to 32 mhz, the consumption is: 290 a/mhz in range 2 (full v dd range), with a maximum cpu frequency of 16 mhz, the consumption is: 235 a/mhz in range 3 (full v dd range), with a maximum cpu frequency limited to 4 mhz (generated only with the multispeed inte rnal rc oscillator clock source), the consumption is: 200 a/mhz. seven low power modes are provided to achieve the best compromise between low power consumption, short startup time and available wakeup sources: sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. the sleep mode power consumption at 16 mhz is of about 1 ma with all peripherals off. low power run mode this mode is achieved with the multispeed internal (msi) rc oscillator set to the minimum clock (64 khz), execution from sram or flash memory, and internal regulator in low power mode to minimize the regulator's operating current. in the low power run mode, the clock frequency and the number of enabled peripherals are both limited. the low power run mode consumption can be as low as 10.5 a when executing code from ram at 32 khz. low power sleep mode this mode is achieved by entering the sleep mode with the internal voltage regulator in low power mode to minimize the regulator?s operating current. in the low power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 khz. when wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on. the low power sleep mode consumption is as low as 4 a when no peripheral is enabled. it is of 5 a with one timer operating at 32 khz. stop mode (with or without rtc) the stop mode achieves the lowest power consumption while retaining the ram and register contents. all clocks in the v core domain are stopped, the pll, msi rc, hsi rc and hse crystal oscillators are disabled. the voltage regulator is in the low power mode. the device can be woken up from the stop mode by any of the exti line, in 8 s. the exti line source can be one of the 16 external lines, the pvd output, the rtc alarm(s), the usb wakeup, the rtc tamper event, the rtc timestamp event, the rtc wakeup, the comparator 1 event or comparator 2 event. the stop mode consumption with the rtc on the lse is of 1.3 a (at 1.8 v) and 1.6 a (at 3.0 v). the stop mode consumption without the rtc is of 0.5 a. standby mode (with or without rtc) the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire v core domain is powered off. the functional overview stm32l151xx, stm32l152xx 14/106 doc id 17659 rev 1 pll, msi rc, hsi rc and hse cr ystal oscillators are also s witched off. af ter entering standby mode, the ram and register contents are lost except for registers in the standby circuitry (wakeup logic, iwdg, rtc, lsi, lse crystal 32k osc, rcc csr). the device exits the standby mode in 60 s when an external reset (nrst pin), an iwdg reset, a rising edge on one of the three wkup pins, rtc alarm (alarm a or alarm b), rtc tamper event, rtc timestamp event or rtc wakeup event. the standby mode consumption is of 1a (at 1.8 v) and 1.3 a (at 3.0 v) with the rtc on, and of 270 na with the rtc off. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering the stop or standby mode. 3.2 arm ? cortex?-m3 core with mpu the arm cortex?-m3 processor is the latest generation of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm cortex?-m3 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the memory protection unit (mpu) improves system re liability by defining the memory attributes (such as read/write access permission s) for different memory regions. it provides up to eight different regions and an optional predefined background region. owing to its embedded arm core, the stm32l15xxx is compatible with all arm tools and software. nested vectored interrupt controller (nvic) the ultralow power stm32l15xxx embeds a ne sted vectored interrupt controller able to handle up to 45 maskable interrupt channels (not including the 16 interrupt lines of cortex?-m3) and 16 priority levels. closely coupled nvic gives low-latency interrupt processing interrupt entry vector table address passed directly to the core closely coupled nvic core interface allows early processing of interrupts processing of late arriving , higher-priority interrupts support for tail-chaining processor state automatically saved interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. stm32l151xx, stm32l152xx functional overview doc id 17659 rev 1 15/106 3.3 reset and supply management 3.3.1 power supply schemes v dd = 1.65 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. v ssa , v dda = 1.65 to 3.6 v: external analog power supplies for adc, reset blocks, rcs and pll (minimum voltage to be applied to v dda is 1.8 v when the adc is used). v dda and v ssa must be connected to v dd and v ss , respectively. 3.3.2 power supply supervisor the device has an integrated zeropower power-on reset (por)/power-down reset (pdr) that can be coupled with a brownout reset (bor) circuitry. for devices operating between 1.8 and 3.6 v, the bor is always active at power-on and ensures proper operation starting from 1.8 v. after the 1.8 v bor threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable bor permanently (in which case, the v dd min value at power down is 1.65 v). five bor thresholds are available through option bytes, starting from 1.8 v to 3 v. to reduce the power consumption in stop mode, it is possib le to automatically switch off the internal reference voltage (v refint ) in stop mode. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for any external reset circuit. note: the start-up time at power-on is typically 3.3 ms. for devices operating between 1.65 v and 3.6 v, the bor is permanently disabled. consequently, the start-up time at power-on can be decreased down to 1ms typically. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. this pvd offers 7 different levels between 1.85 v and 3.05 v, chosen by software, with a step around 200 mv. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.3.3 voltage regulator the regulator has three operation modes: main (mr), low power (lpr) and power down. mr is used in run mode (nominal regulation) lpr is used in the low-power run, low-power sleep and stop modes power down is used in standby mode: the regulator output is high impedance: the kernel circuitry is powered down, inducing ze ro consumption (but the contents of the registers and ram are lost are lost except for the standby circuitry (wakeup logic, iwdg, rtc, lsi, lse crystal 32k osc, rcc csr) 3.3.4 boot modes at startup, boot pins are used to select one of three boot options: boot from flash memory boot from system memory boot from embedded ram functional overview stm32l151xx, stm32l152xx 16/106 doc id 17659 rev 1 the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1 or usart2. for further details please refer to an2606. 3.4 clock management the clock controller distributes the clocks coming from different oscilla tors to the core and the peripherals. it also manages clock gating for low power modes and ensures clock robustness. it features: clock prescaler : to get the best tradeoff between speed and current consumption, the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler safe clock switching : clock sources can be changed safely on the fly in run mode through a configuration register. clock management : to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. master clock source : three different clock sources can be used to drive the master clock: ? 1-24 mhz high-speed external crystal (hse), that can supply a pll ? 16 mhz high-speed internal rc oscillator (hsi), trimmabl e by software, that can supply a pll ? multispeed internal rc oscillator (msi), tr immable by software, able to generate 7 frequencies (64 khz, 128 khz, 256 khz, 512 khz, 1.02 mhz, 2.05 mhz, 4.1 mhz) with a consumption proportional to speed, down to 750 na typical. when a 32.768 khz clock source is available in the system (lse), the msi frequency can be trimmed by software down to a 0.5% accuracy. auxiliary clock source : two ultralow power clock sources that can be used to drive the lcd controller and the real-time clock: ? 32.768 khz low-speed external crystal (lse) ? 37 khz low-speed internal rc (lsi), also used to drive the independent watchdog. the lsi clock can be measur ed using the high-s peed internal rc oscillator for greater precision. rtc and lcd clock sources: the lsi, lse or hse sources can be chosen to clock the rtc and the lcd, whatever the system clock. usb clock source: the embedded pll has a dedicated 48 mhz clock output to supply the usb interface. startup clock : after reset, the microcontroller restarts by default with an internal 2 mhz clock (msi). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. clock security system (css): this feature can be enabled by software. if a hse clock failure occurs, the master clock is automatically switched to hsi and a software interrupt is generated if enabled. clock-out capability (mco: microcontroller clock output): it outputs one of the internal clocks for external use by the application. several prescalers allow the configuration of the ahb frequency, the high-speed apb (apb2) and the low-speed apb (apb1) domains. the maximum freque ncy of the ahb and the apb domains is 32 mhz. see figure 2 for details on the clock tree. stm32l151xx, stm32l152xx functional overview doc id 17659 rev 1 17/106 figure 2. clock tree 3. for the usb function to be available, both hse and pll must be enabled, with the cpu running at either 24 mhz or 32 mhz. 3.5 low power real-time clock and backup registers the real-time clock (rtc) is an independent bcd timer/counter. dedicated registers contain the second, minute, hour (12/24 hour), week day, date, month, year, in bcd (binary-coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day of the month are made ( 3 % / 3 # - ( z / 3 # ? ) . / 3 # ? / 5 4 / 3 # ? ) . / 3 # ? / 5 4 , 3 % / 3 # k ( z ( 3 ) 2 # - ( z , 3 ) 2 # k ( z t o ) n d e p e n d e n t 7 a t c h d o g ) 7 $ ' x x x x x x x 0 , , 0 , , - 5 , ( 3 % ( i g h s p e e d e x t e r n a l c l o c k s i g n a l , 3 % , o w s p e e d e x t e r n a l c l o c k s i g n a l , 3 ) , o w s p e e d i n t e r n a l c l o c k s i g n a l ( 3 ) ( i g h s p e e d i n t e r n a l c l o c k s i g n a l , e g e n d - # / ! ( " 0 r e s c a l e r 0 , , # , + ( 3 ) ( 3 % ! 0 " 0 r e s c a l e r 0 # , + ( # , + 0 , , # , + t o ! ( " b u s c o r e m e m o r y a n d $ - ! 5 3 " # , + t o 5 3 " i n t e r f a c e , 3 % , 3 ) ( 3 ) ( 3 ) ( 3 % p e r i p h e r a l s t o ! 0 " 0 e r i p h e r a l # l o c k % n a b l e % n a b l e 0 e r i p h e r a l # l o c k ! 0 " 0 r e s c a l e r 0 # , + t o 4 ) - a n d p e r i p h e r a l s t o ! 0 " 0 e r i p h e r a l # l o c k % n a b l e % n a b l e 0 e r i p h e r a l # l o c k - ( z - ( z m a x - ( z - ( z m a x t o 2 4 # 0 , , 3 2 # 3 7 - # / 3 % , # 3 3 t o # o r t e x 3 y s t e m t i m e r # l o c k % n a b l e 3 9 3 # , + m a x 2 4 # # , + 2 4 # 3 % , ; = 4 ) - x # , + 4 ) - x # , + ) 7 $ ' # , + 3 9 3 # , + & # , + # o r t e x f r e e r u n n i n g c l o c k t o 4 ) - a n d t o ! $ # 0 e r i p h e r a l c l o c k e n a b l e ! $ # # , + a i c ) f ! 0 " p r e s c a l e r x e l s e x ) f ! 0 " p r e s c a l e r x e l s e x - 3 ) 2 # - 3 ) 0 , , 6 # / - 3 ) , 3 % , 3 ) t o , # $ - 3 ) - u l t i s p e e d i n t e r n a l c l o c k s i g n a l - ( z m a x x x t o 4 i m e r % 4 2 functional overview stm32l151xx, stm32l152xx 18/106 doc id 17659 rev 1 automatically. the rtc provides a programmable alarm and programmable periodic interrupts with wakeup from stop and standby modes. the programmable wakeup time ranges from 120 s to 36 hours stop mode consumption with lsi and auto-wakeup: 1.2 a (at 1.8 v) and 1.4 a (at 3.0 v) stop mode consumption with lse, calendar and auto-wakeup: 1.3 a (at 1.8v), 1.6 a (at 3.0 v) the rtc can be calibrated with an external 512 hz output, and a digital compensation circuit helps reduce drift due to crystal deviation. there are twenty 32-bit backup registers provided to store 80 bytes of user application data. they are cleared in case of tamper detection. 3.6 gpios (general-purpose inputs/outputs) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated afio registers. all gpios are high-current-capable except for analog pins. the alternate function configurat ion of i/os can be locked if needed following a specific sequence in order to avoid spurious writing to the i/o registers. the i/o controller is connected to the ahb with a toggling speed of up to 16 mhz. external interrupt/event controller (exti) the external interrupt/event controller consists of 23 edge detector lines used to generate interrupt/event requests. each line can be individually configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 cloc k period. up to 83 gp ios can be connected to the 16 external interrupt lines. stm32l151xx, stm32l152xx functional overview doc id 17659 rev 1 19/106 3.7 memories the stm32l15xxx devices have the following features: up to 16 kbyte of embedded ram accessed (read/write) at cpu clock speed with 0 wait states. with the enhanced bus matrix, operating the ram does not lead to any performance penalty during accesses to the system bus (ahb and apb buses). the non-volatile memory is divided into three arrays: ? 64 or 128 kbyte of embedded flash program memory ? 4 kbyte of data eeprom ? options bytes the options bytes are used to write-protect the memory (with 4 kb granularity) and/or readout-protect the whole memory with the following options: ? level 0: no readout protection ? level 1: memory readout protection, the flash memory cannot be read from or written to if either debug features are connected or boot in ram is selected ? level 2: chip readout protection, debug features (cortex-m3 jtag and serial wire) and boot in ram selection disabled (jtag fuse) the whole non-volatile memory embeds the error correction code (ecc) feature. 3.8 dma (direct memory access) the flexible 7-channel, general-purpose dma is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with software trigger support for each channel. configuration is done by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, general-purpose timers and adc. 3.9 lcd (liquid crystal display) the lcd drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels. internal step-up converter to guarantee functionality and contrast control irrespective of v dd . this converter can be deactivated, in which case the v lcd pin is used to provide the voltage to the lcd supports static, 1/2, 1/3, 1/4 and 1/8 duty supports static, 1/2, 1/3 and 1/4 bias phase inversion to reduce power consumption and emi up to 8 pixels can be programmed to blink unneeded segments and common pins can be used as general i/o pins lcd ram can be updated at any time owing to a double-buffer the lcd controller can operate in stop mode functional overview stm32l151xx, stm32l152xx 20/106 doc id 17659 rev 1 3.10 adc (analog-to-digital converter) a 12-bit analog-to-digital converters is embedded into stm32l15xxx devices with up to 24 external channels, performing conversions in single-shot or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the general-purpose timers (timx) can be internally connected to the adc start trigger and injection trigger, to allow the applicatio n to synchronize a/d conversions and timers. the adc includes a specific low power mode. the converter is able to operate at maximum speed even if the cpu is operating at a very low frequency and has an auto-shutdown function. the adc?s runtime and analog front-end current consumption are thus minimized whatever the mcu operating mode. temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 1.8 v < v dda < 3.6 v. the temperature sensor is internally connected to the adc_in16 input channel. 3.11 dac (digital-to-analog converter) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration. this dual digital interface supports the following features: two dac converters: one for each output channel up to 10-bit output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual dac channels? independent or simultaneous conversions dma capability for each channel (inc luding the underrun interrupt) external triggers for conversion input reference voltage v ref+ eight dac trigger inputs are used in the stm32l15xxx. the dac channels are triggered through the timer update outputs that are also connected to different dma channels. stm32l151xx, stm32l152xx functional overview doc id 17659 rev 1 21/106 3.12 ultralow power comparators and reference voltage the stm32l15xxx embeds two comparators sharing the same current bias and reference voltage. the reference voltage can be internal or external (coming from an i/o). one comparator with fixed threshold one comparator with rail-to-rail inputs, fast or slow mode. the threshold can be one of the following: ? dac output ? external i/o ? internal reference voltage (v refint ) or v refint submultiple (1/4, 1/2, 3/4) both comparators can wake up from stop mode, and be combined into a window comparator. the internal reference voltage is available externally via a low power / low current output buffer (driving current ca pability of 1 a typical). 3.13 routing interface this interface controls the internal routing of i/os to tim2, tim3, tim4 and to the comparator and reference voltage output. 3.14 timers and watchdogs the ultralow power stm32l15xxx devices incl ude six general-purpose timers, two basic timers and two watchdog timers. ta bl e 3 compares the features of the general-purpose and basic timers. 3.14.1 general-purpose timers (tim2, tim3, tim4, tim9, tim10 and tim11) there are six synchronizable general-purpose timers embedded in the stm32l15xxx devices (see ta bl e 3 for differences). table 3. timer feature comparison timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs tim2, tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 n o tim9 16-bit up any integer between 1 and 65536 no 2 no tim10, tim11 16-bit up any integer between 1 and 65536 no 1 no tim6, tim7 16-bit up any integer between 1 and 65536 ye s 0 n o functional overview stm32l151xx, stm32l152xx 22/106 doc id 17659 rev 1 tim2, tim3, tim4 these timers are based on a 16-bit auto-rel oad up/downcounter and a 16-bit prescaler. they feature 4 independent channels each for input capture/output compare, pwm or one- pulse mode output. this gives up to 12 input captures/output compares/pwms on the largest packages. the tim2, tim3, tim4 general-purpose timers can work together or with the tim10, tim11 and tim9 general-purpose timers via the time r link feature for synchronization or event chaining. their counter can be frozen in debug mode. any of the general-purpose timers can be used to generate pwm outputs. tim2, tim3, tim4 all have independent dma request generation. these timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. tim10, tim11 and tim9 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim10 and tim11 feature one independent channel, whereas tim9 has two independent channels for input capture/output compare, pwm or one-pulse mode output. they can be synchronized with the tim2, tim3, tim4 full-featured general-purpose timers. they can also be used as simple time bases and be clocked by the lse clock source (32.768 khz) to provide time bases independent from the main cpu clock. 3.14.2 basic timers (tim6 and tim7) these timers are mainly used for dac trigger generation. they can also be used as generic 16-bit time bases. 3.14.3 systick timer this timer is dedicated to the os, but could also be used as a standard downcounter. it is based on a 24-bit downcounter with autorel oad capability and a programmable clock source. it features a maskable system interrupt generation when the counter reaches 0. 3.14.4 independent watchdog (iwdg) the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 37 khz internal rc and, as it operates independently of the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. the counter can be frozen in debug mode. 3.14.5 window watchdog (wwdg) the window watchdog is based on a 7-bit downc ounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrup t capability and the counter can be frozen in debug mode. stm32l151xx, stm32l152xx functional overview doc id 17659 rev 1 23/106 3.15 communication interfaces 3.15.1 i2c bus up to two i2c bus interfaces can operate in multimaster and slave modes. they can support standard and fast modes. they support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master mode. a hardware crc generation/verification is embedded. they can be served by dma and they support sm bus 2.0/pm bus. 3.15.2 universal synchronous/asynch ronous receiver tr ansmitter (usart) all usart interfaces are able to communicate at speeds of up to 4 mbit/s. they provide hardware management of the cts and rts signals. they support irda sir endec, are iso 7816 compliant and have lin master/slave capability. all usart interfaces can be served by the dma controller. 3.15.3 serial peripheral interface (spi) up to two spis are able to communicate at up to 16 mbits/s in slave and master modes in full-duplex and simplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card/mmc modes. both spis can be served by the dma controller. 3.15.4 universal serial bus (usb) the stm32l15xxx embeds a usb device peripheral compatible with the usb full-speed 12 mbit/s. the usb interface implements a full-speed (12 mbit/s) function interface. it has software-configurable endpoint setting and supports suspend/resume. the dedicated 48 mhz clock is generated from the internal main pll (the clock source must use a hse crystal oscillator). 3.16 crc (cyclic redundancy check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc ca lculation unit helps co mpute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. functional overview stm32l151xx, stm32l152xx 24/106 doc id 17659 rev 1 3.17 development support serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. the jtag port can be permanently disabled with a jtag fuse. embedded trace macrocell? the arm ? embedded trace macrocell pr ovides a greater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32l15xxx through a small number of etm pi ns to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using usb, ethernet, or any other high-speed channel. real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. tpa hardware is commercially available from common development tool vendors. it operates with third party debugger software tools. stm32l151xx, stm32l152xx pin descriptions doc id 17659 rev 1 25/106 4 pin descriptions figure 3. stm32l15xxx ufbga100 ballout a i17096d a b e d c f g h j k l m pe 3 o s c_in pc15 o s c 3 2_out pc14 rtc_af1 wkup2 pe4 o s c_out pc0 v ss a vref- vref+ vdda pe1 pe5 pe2 pe6 wukp 3 vlcd v ss _5 vdd_5 nr s t pc1 pc 3 pa 0 wkup1 pa 1 pb 8 pe0 pb9 v ss _ 3 v ss _4 vdd_4 pc2 pa 2 pa 3 pa 4 boot0 pb7 vdd_ 3 pa 5 pa 6 pa 7 pd7 pb6 pb5 pc4 pc5 pb0 pd5 pd6 pb2 pb1 pb4 pd4 pe 8 pe7 pb 3 pd 3 pd2 pd9 pe10 pe9 pa15 pd1 pd0 pd 8 pe12 pe11 pa14 pc12 pc11 pc 8 pa 9 pd15 pd12 pb15 pb10 pe1 3 pa 1 3 pc10 ph2 pa 8 pc7 pd14 pd11 pb14 pb11 pe14 v ss _2 vdd_2 pa12 pa11 pa10 pc9 pc6 pd1 3 pd10 pb1 3 pb12 pe15 v ss _1 vdd_1 2 3 4 5 6 7 8 9 10 11 12 1 pc1 3 ph0 ph1 o s c 3 2_in pin descriptions stm32l151xx, stm32l152xx 26/106 doc id 17659 rev 1 figure 4. stm32l15xxx tfbga64 ballout ai16090 b pb2 pc14- o s c 3 2_in pa7 pa4 pa2 pa15 pb11 pb1 pa6 pa 3 h pb10 pc5 pc4 d pa 8 pa9 boot0 pb 8 c pc9 pa11 pb6 pc12 v dda pb9 b pa12 pc10 pc15- o s c 3 2_out pb 3 pd2 a 8 7 6 5 4 3 2 1 v ss _4 o s c_in o s c_out v dd_4 g f e pc2 v ref+ pc1 3 - rtc_af1 pb4 pa1 3 pa14 pb7 pb5 v ss _ 3 pc7 pc 8 pc0 nr s t pc1 pb0 pa5 pb14 v dd_2 v dd_ 3 pb1 3 vlcd pc11 pa10 v ss _2 v ss _1 pc6 v ss a pa1 v dd_1 pb15 pb12 pa0-wkup1 ph0- ph1- - wkup2 stm32l151xx, stm32l152xx pin descriptions doc id 17659 rev 1 27/106 figure 5. stm32l15xxx lqfp100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 vdd_2 vss_2 ph2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 vss_1 vdd_1 vdd_3 vss_3 pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa15 pa14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pe2 pe3 pe4 pe5 pe6-wkup3 v lcd pc13-rtc_af1-wkup2 pc14-osc32_in pc15-osc32_out vss_5 vdd_5 ph0-osc_in ph1-osc_out nrst pc0 pc1 pc2 pc3 vssa vref- vref+ vdda pa 0 - w k u p1 pa 1 pa 2 ai15692b lqfp100 pin descriptions stm32l151xx, stm32l152xx 28/106 doc id 17659 rev 1 figure 6. stm32l15xxx lqfp64 pinout figure 7. stm32l15xxx lqfp48 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v lcd pc13-rtc_af1-wkup2 pc14-osc32_in pc15-osc32_out ph0 -osc_in ph1- osc_out nrst pc0 pc1 pc2 pc3 vssa vdda pa 0 - w k u p1 pa 1 pa 2 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa 1 5 pa 1 4 vdd_2 vss_2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 lqfp64 ai15693b 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 vdd_2 vss_2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pb15 pb14 pb13 pb12 v lcd pc13 - rtc_af1-wkup2 pc14-osc32_in pc15-osc32_out ph0-osc_in ph1-osc_out nrst vssa vdda pa 0 -w k u p1 pa 1 pa 2 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pa 1 5 pa 1 4 lqfp48 ai15694 b stm32l151xx, stm32l152xx pin descriptions doc id 17659 rev 1 29/106 figure 8. stm32l15xxx vfqfpn48 pinout v ss_3 boot0 pb7 pb6 pb5 pb4 pb3 pa15 pa14 48 47 46 45 44 43 42 41 40 1 36 v dd_2 2 35 v ss_2 3 34 pa13 4 vfqpn48 33 pa12 v ssa 5 32 pa11 v dda 6 31 pa10 pa0-wkup 7 30 pa 9 pa 1 8 29 pa 8 pa 2 9 28 v dd_1 13 14 15 16 17 18 19 20 21 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 v ss_1 ai15695b 10 11 12 27 26 25 22 23 24 39 38 37 pb10 pb11 pb15 pb14 pb13 pb12 v lcd pc13-rtc_af1 pc14-osc32_in pc15-osc32_out ph0-osc_in ph1-osc_out nrst pb9 pb8 v dd_3 pin descriptions stm32l151xx, stm32l152xx 30/106 doc id 17659 rev 1 table 4. stm32l15xxx pin definitions pins pin name type (1) i/o level (2) main function (3) (after reset) alternate functions lqfp100 lqfp64 tfbga64 ufbga100 lqfp48 or vfqfpn48 1 - b2 - pe2 i/o ft pe2 traceck/lcd_seg38/tim3_etr 2 - a1 - pe3 i/o ft pe3 traced 0/lcd_seg39/tim3_ch1 3 - b1 - pe4 i/o ft pe4 traced1/tim3_ch2 4 - c2 - pe5 i/o ft pe5 traced2/tim9_ch1 5 - d2 - pe6 i/o ft pe6 traced3/wkup3/tim9_ch2 6 1 b2 e2 1 v lcd (4) sv lcd 72a2c1 2 pc13- rtc_af1 i/o ft pc13 rtc_af1/wkup2 83a1d1 3 pc14- osc32_in i/o pc14 osc32_in 9 4 b1 e1 4 pc15- osc32_out i/o pc15 osc32_out 10 - - f2 - v ss_5 sv ss_5 11 - - g2 - v dd_5 sv dd_5 12 5 c1 f1 5 ph0- osc_in (5) iosc_in ph0 13 6 d1 g1 6 ph1- osc_out o osc_out ph1 14 7 e1 h2 7 nrst i/o nrst 15 8 e3 h1 - pc0 i/o ft pc0 adc_in10/lcd_seg18/ comp1_inp 16 9 e2 j2 - pc1 i/o ft pc1 adc_in11/lcd_seg19/ comp1_inp 17 10 f2 j3 - pc2 i/o ft pc2 adc_in12/lcd_seg20/ comp1_inp 18 11 - (6) k2 - pc3 i/o ft pc3 adc_in13/lcd_seg21/ comp1_inp 19 12 f1 j1 8 v ssa sv ssa 20 - - k1 - v ref- sv ref- 21 - g1 (6) l1 - v ref+ sv ref+ 22 13 h1 m1 9 v dda sv dda 23 14 g2 l2 10 pa0-wkup1 i/o ft pa0 wkup1/usart2_cts/adc_in0/tim2_ch1_etr/ comp1_inp stm32l151xx, stm32l152xx pin descriptions doc id 17659 rev 1 31/106 24 15 h2 m2 11 pa1 i/o ft pa1 usart2_rts/adc_in1/ tim2_ch2/lcd_seg0/ comp1_inp 25 16 f3 k3 12 pa2 i/o ft pa2 usart2_tx/adc_in2/ tim2_ch3/tim9_ch1/ lcd_seg1/comp1_inp 26 17 g3 l3 13 pa3 i/o ft pa3 usart2_rx/adc_in3/tim2_ch4/tim9_ch2/ lcd_seg2/comp1_inp 27 18 c2 e3 - v ss_4 sv ss_4 28 19 d2 h3 - v dd_4 sv dd_4 29 20 h3 m3 14 pa4 i/o pa4 spi1_nss/ usart2_ck/ adc_in4/dac_out1/comp1_inp 30 21 f4 k4 15 pa5 i/o pa5 spi1_sck/adc_in5/ dac_out2/tim2_ch1_etr/comp1_inp 31 22 g4 l4 16 pa6 i/o ft pa6 spi1_miso/adc_in6/tim3_ch1/tim1_bkin/ lcd_seg3/tim10_ch1/ comp1_inp 32 23 h4 m4 17 pa7 i/o ft pa7 spi1_mosi/adc_in7/tim3_ch2/tim1_ch1n/ lcd_seg4/tim11_ch1/comp1_inp 33 24 h5 k5 - pc4 i/o ft pc4 adc_in14/lcd_seg22/comp1_inp 34 25 h6 l5 - pc5 i/o ft pc5 adc_in15/lcd_seg23/comp1_inp 35 26 f5 m5 18 pb0 i/o ft pb0 adc_in8/tim3_ch3/lcd_seg5/ comp1_inp/vref_out 36 27 g5 m6 19 pb1 i/o ft pb1 adc_in9/tim3_ch4/lcd_seg6/ comp1_inp/vref_out 37 28 g6 l6 20 pb2 i/o ft pb2/boot1 38 - - m7 - pe7 i/o pe7 adc_in22/comp1_inp 39 - - l7 - pe8 i/o pe8 adc_in23/comp1_inp 40 - - m8 - pe9 i/o pe9 adc_in24/tim2_ch1_etr/comp1_inp 41 - - l8 - pe10 i/o pe10 adc_in25/tim2_ch2/comp1_inp 42 - - m9 - pe11 i/o ft pe11 tim2_ch3 43 - - l9 - pe12 i/o ft pe12 tim2_ch4/spi1_nss 44 - - m10 - pe13 i/o ft pe13 spi1_sck 45 - - m11 - pe14 i/o ft pe14 spi1_miso 46 - - m12 - pe15 i/o ft pe15 spi1_mosi table 4. stm32l15xxx pin definitions (continued) pins pin name type (1) i/o level (2) main function (3) (after reset) alternate functions lqfp100 lqfp64 tfbga64 ufbga100 lqfp48 or vfqfpn48 pin descriptions stm32l151xx, stm32l152xx 32/106 doc id 17659 rev 1 47 29 g7 l10 21 pb10 i/o ft pb10 i2c2_scl/usart3_tx/tim2_ch3/lcd_seg10 48 30 h7 l11 22 pb11 i/o ft pb11 i2c2_sda/ usart3_rx/tim2 _ch4/lcd_seg11 49 31 d6 f12 23 v ss_1 sv ss_1 50 32 e6 g12 24 v dd_1 sv dd_1 51 33 h8 l12 25 pb12 i/o ft pb12 spi2_nss/i2c2_smba/u sart3_ck/lcd_seg12/ adc_in18/comp1_inp/tim10_ch1 52 34 g8 k12 26 pb13 i/o ft pb13 spi2_sck/usart3_cts/l cd_seg13/adc_in19/ comp1_inp/tim9_ch1 53 35 f8 k11 27 pb14 i/o ft pb14 spi2_miso/ usart3_rts/lcd_seg14/adc_in20/ comp1_inp/tim9_ch2 54 36 f7 k10 28 pb15 i/o ft pb15 spi2_mosi/tim1_ch3n/lcd_seg15/adc_in21/ comp1_inp/tim11_ch1/rtc_50_60hz 55 - - k9 - pd8 i/o ft pd8 usart3_tx/lcd_seg28 56 - - k8 - pd9 i/o ft pd9 usart3_rx/lcd_seg29 57 - - j12 - pd10 i/o ft pd10 usart3_ck/lcd_seg30 58 - - j11 - pd11 i/o ft pd11 usart3_cts/lcd_seg31 59 - - j10 - pd12 i/o ft pd12 tim4_ch1 / usart3_rts/ lcd_seg32 60 - - h12 - pd13 i/o ft pd13 tim4_ch2/lcd_seg33 61 - - h11 - pd14 i/o ft pd14 tim4_ch3/lcd_seg34 62 - - h10 - pd15 i/o ft pd15 tim4_ch4/lcd_seg35 63 37 f6 e12 - pc6 i/o ft pc6 tim3_ch1/lcd_seg24 64 38 e7 e11 pc7 i/o ft pc7 tim3_ch2/lcd_seg25 65 39 e8 e10 pc8 i/o ft pc8 tim3_ch3/lcd_seg26 66 40 d8 d12 - pc9 i/o ft pc9 tim3_ch4/lcd_seg27 67 41 d7 d11 29 pa8 i/o ft pa8 usart1_ck/mco/lcd_com0 68 42 c7 d10 30 pa9 i/o ft pa9 usart1_tx / lcd_com1 69 43 c6 c12 31 pa10 i/o ft pa10 usart1_rx / lcd_com2 70 44 c8 b12 32 pa11 i/o ft pa11 u sart1_cts/ usbdm/spi1_miso 71 45 b8 a12 33 pa12 i/o ft pa12 usart1_rts/usbdp/spi1_mosi 72 46 a8 a11 34 pa13 i/o ft jtms/swdio pa13 table 4. stm32l15xxx pin definitions (continued) pins pin name type (1) i/o level (2) main function (3) (after reset) alternate functions lqfp100 lqfp64 tfbga64 ufbga100 lqfp48 or vfqfpn48 stm32l151xx, stm32l152xx pin descriptions doc id 17659 rev 1 33/106 73 - - c11 - ph2 i/o ft ph2 i2c2_smba 74 47 d5 f11 35 v ss_2 sv ss_2 75 48 e5 g11 36 v dd_2 sv dd_2 76 49 a7 a10 37 pa14 i/o ft jtck/swclk pa14 77 50 a6 a9 38 pa15 i/o ft jtdi tim2_ch1_etr/ pa15/spi1_nss/lcd_seg17 78 51 b7 b11 - pc10 i/o ft pc10 usart3_tx/lcd_ seg28/lcd_seg40/ lcd_com4 79 52 b6 c10 - pc11 i/o ft pc11 usart3_r x/lcd_seg29/lcd_seg41/lcd_com5 80 53 c5 b10 - pc12 i/o ft pc12 usart3_c k/lcd_seg30/lcd_seg42/lcd_com6 81 5 c1 c9 5 pd0 i/o ft osc_in spi2_nss/tim9_ch1 82 6 d1 b9 6 pd1 i/o ft osc_out spi2_sck 83 54 b5 c8 pd2 i/o ft pd2 tim3_etr/lcd_seg31/lcd_seg43/lcd_com7 84 - - b8 - pd3 i/o ft pd3 usart2_cts/spi2_miso 85 - - b7 - pd4 i/o ft pd4 usart2_rts/spi2_mosi 86 - - a6 - pd5 i/o ft pd5 usart2_tx 87 - - b6 - pd6 i/o ft pd6 usart2_rx 88 - - a5 - pd7 i/o ft pd7 usart2_ck/tim9_ch2 89 55 a5 a8 39 pb3 i/o ft jtdo tim2_ch2 / pb3/traceswo spi1_sck/comp2_inm/lcd_seg7 90 56 a4 a7 40 pb4 i/o ft jntrst tim3_ch1/ pb4/ spi1_miso/comp2_inp/lcd_seg8 91 57 c4 c5 41 pb5 i/o ft pb5 i2c1_smbal/tim3_ch2 /spi1_mosi/comp2_inp/lcd_seg9 92 58 d3 b5 42 pb6 i/o ft pb6 i2c1_scl/tim4_ch1/ usart1_tx/lcd_seg8 93 59 c3 b4 43 pb7 i/o ft pb7 i2c1_sda/tim4_ch2/ usart1_rx/pvd_in 94 60 b4 a4 44 boot0 i boot0 95 61 b3 a3 45 pb8 i/o ft pb8 tim4_ch3/i2c1_scl / lcd_seg16/tim10_ch1 96 62 a3 b3 46 pb9 i/o ft pb9 tim4_ch4/i2c1_sda/lcd_com3 / tim11_ch1 97 - - c3 - pe0 i/o ft pe0 tim4_etr/lcd_seg36 /tim10_ch1 table 4. stm32l15xxx pin definitions (continued) pins pin name type (1) i/o level (2) main function (3) (after reset) alternate functions lqfp100 lqfp64 tfbga64 ufbga100 lqfp48 or vfqfpn48 pin descriptions stm32l151xx, stm32l152xx 34/106 doc id 17659 rev 1 98 - - a2 - pe1 i/o ft pe1 lcd_seg37/tim11_ch1 99 63 d4 d3 47 v ss_3 sv ss_3 10 0 64 e4 c4 48 v dd_3 sv dd_3 1. i = input, o = output, s = supply. 2. ft = 5 v tolerant. 3. function availability depends on the chosen device. for devices having reduced peripher al counts, it is always the lower number of peripheral that is included. fo r example, if a device has only one spi and two usarts, they will be called spi1 and usart1 & usart2, respectively. refer to table 2 on page 10 . 4. applicable to stm32l152xx devices only. in stm32l151xx devices, th is pin should be connected to v dd . 5. the pins number 5 and 6 in the lqfp48 and lqfp64 pack ages, and c1 and c2 in the tfbga64 package are configured as osc_in/osc_out after reset, however the functionality of ph0 and ph1 can be remapped by software on these pins. for more details, refer to the alternate function i/o and debug configuration section in the stm32l15xxx reference manual (rm0038). 6. unlike in the lqfp64 package, there is no pc3 in the tfbga64 package. the v ref+ functionality is provided instead. table 4. stm32l15xxx pin definitions (continued) pins pin name type (1) i/o level (2) main function (3) (after reset) alternate functions lqfp100 lqfp64 tfbga64 ufbga100 lqfp48 or vfqfpn48 stm32l151xx, stm32l152xx pin descriptions doc id 17659 rev 1 35/106 table 5. alternate function input/output port name digital alternate function number afio0 afio1 afio2 afio3 afio4 afio5 afoi6 afio7 afio8 a fio9 afio10 afio11 afio12 afio13 afio14 afio15 alternate function system tim2 tim3/4 tim9/10/11 i2c1/2 spi1/2 n/a usart 1/2/3 n/a n/a usbfs lcd n/a n/a ri system boot0 boot0 nrst nrst pa0-wkup1 wkup1 tim2_ch1_ etr usart2_ cts timx_ic1 eventout pa1 tim2_ch2 usart2_ rts [seg0] timx_ic2 eventout pa2 tim2_ch3 tim9_ch1 usart2_ tx [seg1] timx_ic3 eventout pa3 tim2_ch4 tim9_ch2 usart2_ rx [seg2] timx_ic4 eventout pa 4 spi1_nss usart2_ ck timx_ic1 eventout pa 5 tim2_ch1_ etr spi1_sck timx_ic2 eventout pa6 tim3_ch1 tim10_ch1 spi1_m iso [seg3] timx_ic3 eventout pa7 tim3_ch2 tim11_ch1 spi1_m osi [seg4] timx_ic4 eventout pa 8 m c o usart1_ ck [com0] timx_ic1 eventout pa 9 usart1_ tx [com1] timx_ic2 eventout pa 1 0 usart1_ rx [com2] timx_ic3 eventout pa 1 1 spi1_miso usart1_ cts dm timx_ic4 eventout pa 1 2 spi1_mosi usart1_ rts dp timx_ic1 eventout pa13 jtms-swdat timx_ic2 eventout pa14 jtck-swclk timx_ic3 eventout stm32l151xx, stm32l152xx pin descriptions doc id 17659 rev 1 36/106 pa15 jtdi tim2_ch1_ etr spi1_nss seg17 timx_ic4 eventout pb0 tim3_ch3 [seg5] eventout pb1 tim3_ch4 [seg6] eventout pb2 boot1 eventout pb3 jtdo tim2_ch2 spi1_sck [seg7] eventout pb4 jtrst tim3_ch1 spi1_miso [seg8] eventout pb5 tim3_ch2 i2c1_smb al spi1_mosi [seg9] eventout pb6 tim4_ch1 i2c1_scl usart1_ tx eventout pb7 tim4_ch2 i2c1_sda usart1_ rx eventout pb8 tim4_ch3 tim10_ch1 * i2c1_scl seg16 eventout pb9 tim4_ch4 tim11_ch1 * i2c1_sda [com3] eventout pb10 tim2_ch3 i2c2_scl usart3_ tx seg10 eventout pb11 tim2_ch4 i2c2_sda usart3_ rx seg11 eventout pb12 tim10_ch1 i2c2_smb al spi2_nss usart3_ ck seg12 eventout pb13 tim9_ch1 spi2_sck usart3_ cts seg13 eventout pb14 tim9_ch2 spi2_miso usart3_ rts seg14 eventout pb15 rtc 50/60 hz tim11_ch1 spi2_mosi seg15 eventout pc0 seg18 timx_ic1 eventout table 5. alternate function input/output (continued) port name digital alternate function number afio0 afio1 afio2 afio3 afio4 afio5 afoi6 afio7 afio8 a fio9 afio10 afio11 afio12 afio13 afio14 afio15 alternate function system tim2 tim3/4 tim9/10/11 i2c1/2 spi1/2 n/a usart 1/2/3 n/a n/a usbfs lcd n/a n/a ri system pin descriptions stm32l151xx, stm32l152xx 37/106 doc id 17659 rev 1 pc1 seg19 timx_ic2 eventout pc2 seg20 timx_ic3 eventout pc3 seg21 timx_ic4 eventout pc4 seg22 timx_ic1 eventout pc5 seg23 timx_ic2 eventout pc6 tim3_ch1 seg24 timx_ic3 eventout pc7 tim3_ch2 seg25 timx_ic4 eventout pc8 tim3_ch3 seg26 timx_ic1 eventout pc9 tim3_ch4 seg27 timx_ic2 eventout pc10 usart3_ tx com4 / seg28 / seg40 timx_ic3 eventout pc11 usart3_ rx com5 / seg29 / seg41 timx_ic4 eventout pc12 usart3_ ck com6 / seg30 / seg42 timx_ic1 eventout pc13- rtc_af1 rtc_af1 / wkup2 timx_ic2 eventout pc14- osc32_in osc32_in timx_ic3 eventout pc15- osc32_out osc32_out timx_ic4 eventout pd0 tim9_ch1 spi2_nss timx_ic1 eventout pd1 spi2_sck timx_ic2 eventout table 5. alternate function input/output (continued) port name digital alternate function number afio0 afio1 afio2 afio3 afio4 afio5 afoi6 afio7 afio8 a fio9 afio10 afio11 afio12 afio13 afio14 afio15 alternate function system tim2 tim3/4 tim9/10/11 i2c1/2 spi1/2 n/a usart 1/2/3 n/a n/a usbfs lcd n/a n/a ri system pin descriptions stm32l151xx, stm32l152xx 38/106 doc id 17659 rev 1 pd2 tim3_etr com7 / seg31 / seg43 timx_ic3 eventout pd3 spi2_miso usart2_ cts timx_ic4 eventout pd4 spi2_mosi usart2_ rts timx_ic1 eventout pd5 usart2_ tx timx_ic2 eventout pd6 usart2_ rx timx_ic3 eventout pd7 tim9_ch2 usart2_ ck timx_ic4 eventout pd8 usart3_ tx seg28 timx_ic1 eventout pd9 usart3_ rx seg29 timx_ic2 eventout pd10 usart3_ ck seg30 timx_ic3 eventout pd11 usart3_ cts seg31 timx_ic4 eventout pd12 tim4_ch1 usart3_ rts seg32 timx_ic1 eventout pd13 tim4_ch2 seg33 timx_ic2 eventout pd14 tim4_ch3 seg34 timx_ic3 eventout pd15 tim4_ch4 seg35 timx_ic4 eventout pe0 tim4_etr tim10_ch1 seg36 timx_ic1 eventout pe1 tim11_ch1 seg37 timx_ic2 eventout pe2 traceck tim3_etr seg 38 timx_ic3 eventout pe3 traced0 tim3_ch1 seg 39 timx_ic4 eventout table 5. alternate function input/output (continued) port name digital alternate function number afio0 afio1 afio2 afio3 afio4 afio5 afoi6 afio7 afio8 a fio9 afio10 afio11 afio12 afio13 afio14 afio15 alternate function system tim2 tim3/4 tim9/10/11 i2c1/2 spi1/2 n/a usart 1/2/3 n/a n/a usbfs lcd n/a n/a ri system stm32l151xx, stm32l152xx pin descriptions doc id 17659 rev 1 39/106 pe4 traced1 tim3_ch2 timx_ic1 eventout pe5 traced2 tim9_ch1* timx_ic2 eventout pe6 traced3 / wkup3 tim9_ch2* timx_ic3 eventout pe7 timx_ic4 eventout pe8 timx_ic1 eventout pe9 tim2_ch1_ etr timx_ic2 eventout pe10 tim2_ch2 timx_ic3 eventout pe11 tim2_ch3 timx_ic4 eventout pe12 tim2_ch4 spi1_nss timx_ic1 eventout pe13 spi1_sck timx_ic2 eventout pe14 spi1_miso timx_ic3 eventout pe15 spi1_mosi timx_ic4 eventout ph0-osc_in osc_in ph1- osc_out osc_out ph2 eventout table 5. alternate function input/output (continued) port name digital alternate function number afio0 afio1 afio2 afio3 afio4 afio5 afoi6 afio7 afio8 a fio9 afio10 afio11 afio12 afio13 afio14 afio15 alternate function system tim2 tim3/4 tim9/10/11 i2c1/2 spi1/2 n/a usart 1/2/3 n/a n/a usbfs lcd n/a n/a ri system memory mapping stm32l151xx, stm32l152xx 40/106 doc id 17659 rev 1 5 memory mapping the memory map is shown in the following figure. figure 9. memory map reserved 0x4000 0000 0x4000 0400 0x4000 0800 0x4000 0c00 0x4000 2800 0x4000 2c00 0x4000 3000 0x4000 3400 0x4000 3800 0x4000 3c00 0x4000 4400 0x4000 4800 0x4000 4c00 0x4001 0c00 0x4001 1000 0x4001 1400 apb memory space crc 0x4002 3800 tim2 reserved 0x4001 0800 0x4001 2400 0x4001 2800 0x4001 3000 0x4001 3400 0x4001 3800 tim3 tim4 rtc wwdg iwdg reserved spi2 usart2 usart3 syscfg tim9 tim11 rese rve d adc reserved usart1 reserved 0x4002 3400 0x4002 0000 0x4001 3c00 0x4000 5400 0x4000 5800 reserved reserved spi1 i2c1 0x4000 6000 0x4000 5c00 pwr tim10 i2c2 reserved exti reserved rcc flash interface reserved reserved reserved 0x4000 6200 0x4000 7000 0x4000 7400 0x4000 7c00 0x4001 0400 0x4002 3c00 0x4002 4000 0x4002 6000 0x4002 6400 0x6000 0000 0xe010 0000 reserved 0xffff ffff usb reg isters dma 0 1 2 3 4 5 6 7 0x2000 0000 0x4000 0000 0x6000 0000 0x8000 0000 0xa000 0000 0xc000 0000 0xe000 0000 0xffff ffff 0x0000 0000 peripherals sram cortex- m3 internal peripherals 0xe010 0000 ai18200b 512 byte usb tim6 tim7 lcd reserved reserved 0x4000 1000 0x4000 1400 0x4000 2400 0x4000 1c00 dac1 & 2 0x4000 7800 port a port b port c port d port e port h reserved 0x4002 3000 0x4002 1800 0x4002 1400 0x4002 1000 0x4002 0c00 0x4002 0800 0x4002 0400 comp + ri flash memory rese rved rese rved 0x0800 0000 0x0801 ffff 0x1ff0 0000 0x1ff8 001f system memory option bytes 0x1ff0 0fff 0x1ff8 0000 aliased to flash or system memory depending on boot pins 0x0000 0000 rese rved data eeprom rese rved 0x0808 0000 0x0808 0fff 0x4001 0000 reserved reserved stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 41/106 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 1.65 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 10 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 11 . figure 10. pin loading condition s figure 11. pin input voltage a i # p & 3 4 - , x x x p i n a i 3 4 - , x x x p i n 6 ) . electrical characteristics stm32l151xx, stm32l152xx 42/106 doc id 17659 rev 1 6.1.6 power supply scheme figure 12. power supply scheme caution: in this figure, the 4.7 f capacitor must be connected to v dd2 . 6.1.7 current con sumption measurement figure 13. current consumption measurement scheme ai15401c v dd1/2/.../11 an alo g: rcs, pll, ... gp i/o s out in kernel logic (cpu, digital & memories) standby-power circuitry (osc32k,rtc, rtc backup registers) wake-up logic 11 100 nf + 1 4.7 f regulator v ss1/2/.../11 v dda v ref+ v ref- v ssa adc level shifter io logic v dd 10 nf + 1 f v ref 10 nf + 1 f v dd ai14126b v dd v dda i dd stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 43/106 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 6: voltage characteristics , table 7: current characteristics , and table 8: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 6. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda and v dd ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in input voltage on five-volt tolerant pin (2) 2. positive current injection is not possible on these i/os. v in maximum must be respected. negative current injection is possible and must not exceed i inj(pin) . v ss ? 0.3 v dd +4.0 input voltage on any other pin (3) 3. i inj(pin) must never be exceeded (see table 7: current characteristics ). this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v in max while a negative injection is induced by v in < v ss . v ss ? 0.3 4.0 | v ddx | variations between different v dd power pins 50 mv |v ssx ? v ss | variations between all different ground pins 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.10 table 7. current characteristics symbol ratings max. unit i vdd total current into v dd /v dda power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 150 ma i vss total current out of v ss ground lines (sink) (1) 150 i io output current sunk by any i/o and control pin 25 output current sourced by any i/o and control pin - 25 i inj(pin) (2) 2. negative injection disturbs the analog performance of the device. see note in section 6.3.15 . injected current on nrst pin (3) 3. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . 5 injected current on five-volt tolerant i/o (4) 4. positive current injection is not possible on these i/os. v in maximum must be respected. negative current injection is possible and must not exceed i inj(pin) . +0 / -5 injected current on any other pin (3) 5 i inj(pin) total injected current (sum of all i/o and control pins) (5) 25 electrical characteristics stm32l151xx, stm32l152xx 44/106 doc id 17659 rev 1 6.3 operating conditions 6.3.1 general operating conditions 5. when several inputs are submitted to a current injection, the maximum i inj(pin) is the absolute sum of the positive and negative injected currents (insta ntaneous values). thes e results are based on characterization with i inj(pin) maximum current injection on four i/o port pins of the device. table 8. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c table 9. general operating conditions symbol parameter co nditions min max unit f hclk internal ahb clock frequency 0 32 mhz f pclk1 internal apb1 clock frequency 0 32 f pclk2 internal apb2 clock frequency 0 32 v dd standard operating voltage bor detector disabled 1.65 3.6 v bor detector enabled, at power on 1.8 3.6 bor detector disabled, after power on 1.65 3.6 v dda (1) 1. when the adc is used, refer to table 48: adc characteristics . analog operating voltage (adc not used) must be the same voltage as v dd (2) 2. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and operation. 1.65 3.6 v analog operating voltage (adc used) 1.8 3.6 p d power dissipation at t a = 85 c (3) 3. if t a is lower, higher p d values are allowed as long as t j does not exceed t j max (see table 62: thermal characteristics on page 101 ). lqfp100 434 mw lqfp64 444 lqfp48 363 lfbga108 tbd tfbga64 308 vfqfn48 tbd t a temperature range maximum power dissipation ?40 85 c low power dissipation (4) ?40 105 t j junction temperature range -40 c t a 105 c ?40 105 c stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 45/106 4. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t j max (see table 62: thermal characteristics on page 101 ). table 10. functionalities depending on the operating power supply range functionalities depending on the operating power supply range operating power supply range adc operation usb v core maximum cpu frequency (f cpu max) i/o operation v dd = 1.65 to 1.8 v not functional not functional range 2 or range 3 16 mhz (1ws) 8mhz (0ws) - degraded speed performance - no i/o compensation v dd = 1.8 to 2.0 v conversion time up to 500 ksps not functional range 2 or range 3 16 mhz (1ws) 8mhz (0ws) - degraded speed performance - no i/o compensation v dd = 2.0 to 2.4 v conversion time up to 500 ksps functional range 1, range 2 or range 3 32 mhz (1ws) 16mhz (0ws) - full-speed operation - i/o compensation works v dd = 2.4 to 3.6 v conversion time up to 1 msps functional range 1, range 2 or range 3 32 mhz (1ws) 16mhz (0ws) - full-speed operation - i/o compensation works electrical characteristics stm32l151xx, stm32l152xx 46/106 doc id 17659 rev 1 6.3.2 embedded reset and power control block characteristics the parameters given in the following table are derived from the tests performed under the ambient temperature condition summarized in ta b l e 9 . table 11. embedded reset and power control block characteristics symbol parameter conditions min typ max unit t vdd v dd rise time rate bor detector enabled 0 (1) s/v bor detector disabled tbd tbd v dd fall time rate 0 (1) t rsttempo (1) reset temporization v dd rising, bor enabled 3.3 tbd ms v dd rising, bor disabled 1.1 tbd v por/pdr power on/power down reset threshold falling edge tbd 1.5 tbd v rising edge tbd 1.5 tbd v bor0 brown-out reset threshold 0 falling edge tbd 1.7 tbd rising edge tbd 1.76 tbd v bor1 brown-out reset threshold 1 falling edge tbd 1.93 tbd rising edge tbd 2.03 tbd v bor2 brown-out reset threshold 2 falling edge tbd 2.30 tbd rising edge tbd 2.41 tbd v bor3 brown-out reset threshold 3 falling edge tbd 2.55 tbd rising edge tbd 2.66 tbd v bor4 brown-out reset threshold 4 falling edge tbd 2.8 tbd rising edge tbd 2.9 tbd v pvd0 programmable voltage detector threshold 0 falling edge tbd 1.85 tbd rising edge tbd 1.94 tbd v pvd1 pvd threshold 1 falling edge tbd 2.04 tbd rising edge tbd 2.14 tbd v pvd2 pvd threshold 2 falling edge tbd 2.24 tbd rising edge tbd 2.34 tbd v pvd3 pvd threshold 3 falling edge tbd 2.44 tbd rising edge tbd 2.54 tbd v pvd4 pvd threshold 4 falling edge tbd 2.64 tbd rising edge tbd 2.74 tbd v pvd5 pvd threshold 5 falling edge tbd 2.83 tbd rising edge tbd 2.94 tbd v pvd6 pvd threshold 6 falling edge tbd 3.05 tbd rising edge tbd 3.15 tbd stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 47/106 v hyst hysteresis voltage bor0 threshold 40 mv all bor and pvd thresholds excepting bor0 100 1. guaranteed by design, not tested in production. figure 10. power supply thresholds 1. the pvd is available on all stm32l devices and it is enabl ed or disabled by software. 2. the bor is available only on de vices operating from 1.8 to 3.6 v, and unless disabled by option byte it will mask the por/pdr threshold. 3. when the bor is disabled by opt ion byte, the reset is asserted when vdd goes below pdr level 4. for devices operating from 1.65 to 3. 6 v, there is no bor and the reset is released when vdd goes above por level and asserted when vdd goes below pdr level table 11. embedded reset and power control block characteristics (continued) symbol parameter conditions min typ max unit v dd /v dda pvd o u tp u t 100 mv hy s tere s i s v pvd v bor hy s tere s i s 100 mv it en ab led bor re s et (n r s t) por/pdr re s et (nr s t) pvd bor a lw a y s a ctive por/pdr (bor not a v a il ab le) a i17211 b por v / pdr v bor/pdr re s et (nr s t) bor di sab led b y option b yte (note 1) (note 2) (note 3 ) (note 4) electrical characteristics stm32l151xx, stm32l152xx 48/106 doc id 17659 rev 1 6.3.3 embedded internal reference voltage the parameters given in ta bl e 1 2 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . table 12. embedded internal reference voltage symbol parameter conditions min typ max unit v refint out internal reference voltage ?40 c < t j < +105 c tbd 1.224 tbd v i refint internal reference current consumption 1.4 tbd a t vrefint internal reference startup time 2 tbd ms v vref_meas v dda and v ref+ voltage during v refint factory measure built-in adc 2.99 3 3.01 v a vref_meas accuracy of factory-measured v ref value including uncertainties due to adc and v dda /v ref+ values 5 mv v refint (2) internal reference voltage spread over the temperature range v dd = 3 v 10 mv 10 mv t coeff (2) temperature coefficient 20 50 ppm/c a coeff (2) long-term stability 1000 hours, t= 25 c tbd ppm t s_vrefint (1) adc sampling time when reading the internal reference voltage 510 (2) s t adc_buf startup time of reference voltage buffer for adc tbd s i buf_adc consumption of reference voltage buffer for adc 13.5 tbd a i vref_out vref_out output current (3) 1a c vref_out vref_out output load 50 pf i lpbuf consumption of reference voltage buffer for vref_out and comp 730 tbd na v refint_div1 1/4 reference voltage 25 % v refint v refint_div2 1/2 reference voltage 50 v refint_div3 3/4 reference voltage 75 1. shortest sampling time can be determined in the application by multiple iterations. 2. guaranteed by design, not tested in production. 3. to guaranty less than 1% vref_out deviation. stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 49/106 6.3.4 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 13: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to dhrystone 2.1 code. maximum current consumption the mcu is placed under the following conditions: v dd = 3.6v all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except when explicitly mentioned the flash memory access time is adjusted depending on f hclk frequency and voltage range prefetch and 64-bit access are enabled in configurations with 1 wait state the parameters given in ta bl e 1 3 , ta bl e 9 and ta b l e 1 1 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . electrical characteristics stm32l151xx, stm32l152xx 50/106 doc id 17659 rev 1 table 13. current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ max (1) unit 55 c 85 c 105 c i dd (run from flash) supply current in run mode, code executed from flash hse = 16 mhz (2) (pll on for f hclk above 16 mhz) range 3, v core =1.2 v vos[1:0] = 11 1 mhz 234 tbd tbd tbd a 2 mhz 427 tbd tbd tbd 4 mhz 813 tbd tbd tbd range 2, v core =1.5 v vos[1:0] = 10 4 mhz 0.97 tbd tbd tbd ma 8 mhz 1.87 tbd tbd tbd 16 mhz 3.8 tbd tbd tbd range 1, v core =1.8 v vos[1:0] = 01 8 mhz 2.16 tbd tbd tbd 16 mhz 4.57 tbd tbd tbd 32 mhz 9.5 tbd tbd tbd hsi clock source (16 mhz) range 3, v core =1.2 v vos[1:0] = 11 4 mhz tbd tbd tbd tbd range 2, v core =1.5 v vos[1:0] = 10 16 mhz tbd tbd tbd tbd range 1, v core =1.8 v vos[1:0] = 01 32 mhz tbd tbd tbd tbd msi clock, 64 khz range 3, v core =1.2 v vos[1:0] = 11 64 khz tbd tbd tbd tbd msi clock, 512 khz 512 khz tbd tbd tbd tbd msi clock, 4 mhz 4 mhz tbd tbd tbd tbd 1. based on characterization, not tested in production, unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register). stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 51/106 table 14. current consumption in run mode, code with data processing running from ram symbol parameter conditions f hclk typ max (1) unit 55 c 85 c 105 c i dd (run from ram) supply current in run mode, code executed from ram, flash switched off hse = 16 mhz (2) (pll on for f hclk above 16 mhz) range 3, v core =1.2 v vos[1:0] = 11 1 mhz 204 tbd tbd tbd a 2 mhz 380 tbd tbd tbd 4 mhz tbd tbd tbd tbd (3) range 2, v core =1.5 v vos[1:0] = 10 4 mhz 0.9 tbd tbd tbd ma 8 mhz 1.73 tbd tbd tbd 16 mhz 3.5 tbd tbd tbd range 1, v core =1.8 v vos[1:0] = 01 8 mhz 2.01 tbd tbd tbd 16 mhz 4.21 tbd tbd tbd 32 mhz 8.68 tbd tbd tbd hsi clock source (16 mhz) range 3, v core =1.2 v vos[1:0] = 11 4 mhz tbd tbd tbd tbd range 2, v core =1.5 v vos[1:0] = 10 16 mhz tbd tbd tbd tbd range 1, v core =1.8 v vos[1:0] = 01 32 mhz tbd tbd tbd tbd msi clock, 64 khz range 3, v core =1.2 v vos[1:0] = 11 64 khz tbd tbd tbd tbd msi clock, 512 khz 512 khz tbd tbd tbd tbd msi clock, 4 mhz 4 mhz tbd tbd tbd tbd 1. based on characterization, not tested in production, unless otherwise specified. 2. oscillator bypassed (hseb yp = 1 in rcc_cr register) 3. data guaranteed, each individual device tested in production electrical characteristics stm32l151xx, stm32l152xx 52/106 doc id 17659 rev 1 table 15. current consumption in sleep mode symbol parameter conditions f hclk typ max (1) unit 55 c 85 c 105 c i dd (sleep) supply current in sleep mode, code executed from ram, flash switched off hse = 16 mhz (2) (pll on for f hclk >16 mhz) range 3, v core =1.2 v vos[1:0] = 11 1 mhz tbd tbd tbd tbd a 2 mhz tbd tbd tbd tbd 4 mhz tbd tbd tbd tbd (3) range 2, v core =1.5 v vos[1:0] = 10 4 mhz tbd tbd tbd tbd 8 mhz tbd tbd tbd tbd 16 mhz tbd tbd tbd tbd range 1, v core =1.8 v vos[1:0] = 01 8 mhz tbd tbd tbd tbd 16 mhz tbd tbd tbd tbd 32 mhz tbd tbd tbd tbd hsi clock source (16 mhz) range 3, v core =1.2 v vos[1:0] = 11 4 mhz tbd tbd tbd tbd range 2, v core =1.5 v vos[1:0] = 10 16 mhz tbd tbd tbd tbd range 1, v core =1.8 v vos[1:0] = 01 32 mhz tbd tbd tbd tbd msi clock, 64 khz range 3, v core =1.2 v vos[1:0] = 11 64 khz tbd tbd tbd tbd msi clock, 512 khz 512 khz tbd tbd tbd tbd msi clock, 4 mhz 4 mhz tbd tbd tbd tbd supply current in sleep mode, code executed from flash hse = 16 mhz (2) (pll on for f hclk above 16 mhz) range 3, v core =1.2 v vos[1:0] = 11 1 mhz tbd tbd tbd tbd 2 mhz tbd tbd tbd tbd 4 mhz 330 tbd tbd tbd range 2, v core =1.5 v vos[1:0] = 10 4 mhz tbd tbd tbd tbd ma 8 mhz tbd tbd tbd tbd 16 mhz 1.1 tbd tbd tbd range 1, v core =1.8 v vos[1:0] = 01 8 mhz tbd tbd tbd tbd 16 mhz 1.39 tbd tbd tbd 32 mhz 2.61 tbd tbd tbd hsi clock source (16 mhz) range 3, v core =1.2 v vos[1:0] = 11 4 mhz tbd tbd tbd tbd range 2, v core =1.5 v vos[1:0] = 10 16 mhz 1 tbd tbd tbd range 1, v core =1.8 v vos[1:0] = 01 32 mhz 2.16 tbd tbd tbd stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 53/106 i dd (sleep) supply current in sleep mode, code executed from flash msi clock, 64 khz range 3, v core =1.2v vos[1:0] = 11 64 khz 19 tbd tbd tbd a msi clock, 512 khz 512 khz 36 tbd tbd tbd msi clock, 4 mhz 4 mhz 179 tbd tbd tbd 1. based on characterization, not tested in production, unless otherwise specified. 2. oscillator bypassed (hseb yp = 1 in rcc_cr register) 3. data guaranteed, each individual device tested in production table 15. current consumption in sleep mode (continued) symbol parameter conditions f hclk typ max (1) unit 55 c 85 c 105 c table 16. current consumption in low power run mode symbol parameter conditions typ max (1) unit i dd (lp run) supply current in low power run mode all peripherals off, code executed from ram, flash switched off, v dd from 1.65 v to 3.6 v msi clock, 64 khz f hclk = 32 khz t a = 25c 10.5 a msi clock, 64 khz f hclk = 64 khz t a = 25c 15.8 msi clock, 128 khz f hclk = 128 khz t a = -40 c to 25 c tbd tbd t a = 55 c tbd tbd t a = 85 c tbd tbd t a = 105 c tbd tbd all peripherals off, code executed from flash, v dd from 1.65 v to 3.6 v msi clock, 64 khz f hclk = 32 khz t a = 25 c tbd msi clock, 64 khz f hclk = 64 khz t a = 25 c tbd msi clock, 128 khz f hclk = 128 khz t a = -40 c to 25 c tbd tbd t a = 55 c tbd tbd t a = 85 c tbd tbd t a = 105 c tbd tbd i dd max (lp run) max current in low power run mode v dd from 1.65 v to 3.6 v tbd tbd 1. based on characterization, not tested in production, unless otherwise specified. electrical characteristics stm32l151xx, stm32l152xx 54/106 doc id 17659 rev 1 table 17. current consumption in low power sleep mode symbol parameter conditions typ max (1) 1. based on characterization, not tested in production, unless otherwise specified. unit i dd (lp sleep) supply current in low power sleep mode all peripherals off, code executed from flash, v dd from 1.65 v to 3.6 v msi clock, 64 khz f hclk = 32 khz t a = 25 c 4.07 a msi clock, 64 khz f hclk = 64 khz t a = 25 c 4.55 msi clock, 128 khz f hclk = 128 khz t a = -40 c to 25 c 7.69 tbd t a = 55 c tbd tbd t a = 85 c tbd tbd t a = 105 c tbd tbd tim9 and usart1 enabled, code executed from flash, v dd from 1.65 v to 3.6 v msi clock, 64 khz f hclk = 32 khz t a = 25 c 4.85 msi clock, 64 khz f hclk = 64 khz t a = 25 c 5.66 msi clock, 128 khz f hclk = 128 khz t a = -40 c to 25 c 9.85 tbd t a = 55 c tbd tbd t a = 85 c tbd tbd t a = 105 c tbd tbd i dd max (lp run) max current in low power run mode v dd from 1.65 v to 3.6 v tbd tbd stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 55/106 table 18. typical and maximum current consumptions in stop mode symbol parameter conditions typ (1) 1. typical values are measured at t a = 25 c. max unit i dd (stop with rtc) supply current in stop mode with rtc enabled rtc clocked by lsi, regulator in lp mode, hsi and hse off (no independent watchdog) lcd off t a = -40c to 25c 1.3 a t a = 55c tbd t a = 85c tbd t a = 105c tbd lcd on (static duty) (2) t a = -40c to 25c 3.3 t a = 55c tbd t a = 85c tbd t a = 105c tbd lcd on (1/8 duty) (3) t a = -40c to 25c 7.6 t a = 55c tbd t a = 85c tbd t a = 105c tbd rtc clocked by lse external clock (32.768 khz), regulator in lp mode, hsi and hse off (no independent watchdog) lcd off t a = -40c to 25c 1.6 tbd t a = 55c tbd tbd t a = 85c tbd tbd t a = 105c tbd tbd lcd on (static duty) (2) t a = -40c to 25c 3.6 tbd t a = 55c tbd tbd t a = 85c tbd tbd t a = 105c tbd tbd lcd on (1/8 duty) (3) t a = -40c to 25c 7.6 tbd t a = 55c tbd tbd t a = 85c tbd tbd t a = 105c tbd tbd i dd (stop) supply current in stop mode ( rtc disabled) regulator in lp mode, hsi and hse off, independent watchdog and lsi enabled t a = -40c to 25c 1.1 regulator in lp mode, lsi, hsi and hse off (no independent watchdog) t a = -40c to 25c 0.5 tbd t a = 55c tbd tbd t a = 85c tbd tbd t a = 105c tbd tbd i dd (wu from stop) supply current during wake-up from stop mode msi = 4 mhz t a = -40c to 25c tbd msi = 1 mhz tbd msi = 64 khz tbd electrical characteristics stm32l151xx, stm32l152xx 56/106 doc id 17659 rev 1 2. lcd enabled with external vlcd, static duty, divisi on ratio = 256, all pixels active, no lcd connected 3. lcd enabled with external vlcd, 1/4 duty, 1/3 bias, division ratio = 64, all pixe ls active, no lcd connected. table 19. typical and maximum current consumptions in standby mode symbol parameter conditions typ (1) max unit i dd (standby with rtc) supply current in standby mode with rtc enabled rtc clocked by lsi (no independent watchdog) t a = -40 c to 25 c 1.1 a t a = 55 c tbd t a = 85 c tbd t a = 105 c tbd rtc clocked by lse (no independent watchdog) t a = -40 c to 25 c 1.3 tbd t a = 55 c tbd tbd t a = 85 c tbd tbd t a = 105 c tbd tbd i dd (standby) supply current in standby mode (rtc disabled) independent watchdog and lsi enabled t a = -40 c to 25 c 1 a independent watchdog and lsi off t a = -40 c to 25 c 0.3 tbd t a = 55 c tbd tbd t a = 85 c tbd tbd t a = 105 c tbd tbd i dd (wu from stop) supply current during wakeup from stop mode t a = -40 c to 25 c tbd 1. typical values are measured at t a = 25 c. stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 57/106 wakeup time from low-power mode the wakeup times given in the following table are measured on a wakeup phase with the msi rc oscillator. the clock source used to wake up the device d epends on th e current operating mode: sleep mode: the clock source is the clock that was set before entering sleep mode stop mode: the clock source is the msi os cillator in the range configured before entering deep sleep mode standby mode: the clock source is the msi osc illator running at 2 mhz all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 9 . table 20. typical and maximum timings in low power modes symbol parameter conditions typ (1) 1. typical values are measured at t a = 25 c. max unit t wusleep (2) 2. wakeup time until start of interrupt vector fetch. the first word of interrupt routine is fetched n cpu cycles after t wu . wakeup from sleep mode f hclk = 32 mhz 0.35 s t wusleep_lp (2) wakeup from low power sleep mode f hclk = 128 khz f hclk = 128 khz flash enabled tbd f hclk = 128 khz flash switched off tbd t wustop (1) wakeup from stop mode, regulator in run mode f hclk = f hsi = 16 mhz tbd wakeup from stop mode, regulator in low power mode f hclk = f msi = 4.2 mhz voltage range 1 and 2 7.9 tbd f hclk = f msi = 4.2 mhz voltage range 3 7.9 tbd f hclk = f msi = 2.1 mhz 10.2 tbd f hclk = f msi = 1.05 mhz tbd tbd f hclk = f msi = 524 khz tbd tbd f hclk = f msi = 262 khz tbd tbd f hclk = f msi = 131 khz tbd tbd f hclk = msi = 64 khz tbd tbd t wustdby (1) wakeup from standby mode f hclk = msi = 2.1 mhz 57 tbd electrical characteristics stm32l151xx, stm32l152xx 58/106 doc id 17659 rev 1 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in the following table. the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ambient operating temperature and v dd supply voltage conditions summarized in table 6: voltage characteristics . table 21. peripheral current consumption (1) peripheral typical consumption, v dd = 3.0 v, t a = 25 c unit range 1, v core = 1.8 v vos[1:0] = 01 range 2, v core = 1.5 v vos[1:0] = 10 range 3, v core = 1.2 v vos[1:0] = 11 low power sleep and run apb1 tim2 tbd tbd tbd tbd a/mhz tim3 tbd tbd tbd tbd tim4 tbd tbd tbd tbd tim6 tbd tbd tbd tbd tim7 tbd tbd tbd tbd lcd tbd tbd tbd tbd wwdg tbd tbd tbd tbd spi2 tbd tbd tbd tbd usart2 tbd tbd tbd tbd usart3 tbd tbd tbd tbd i2c1 tbd tbd tbd tbd i2c2 tbd tbd tbd tbd usb tbd tbd tbd tbd pwr tbd tbd tbd tbd dac tbd tbd tbd tbd comp tbd tbd tbd tbd usb tbd tbd tbd tbd stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 59/106 apb2 syscfg & ri tbd tbd tbd tbd a/mhz tim9 tbd tbd tbd tbd tim10 tbd tbd tbd tbd tim11 tbd tbd tbd tbd adc1 tbd tbd tbd tbd spi1 tbd tbd tbd tbd usart1 tbd tbd tbd tbd ahb gpioa tbd tbd tbd tbd gpiob tbd tbd tbd tbd gpioc tbd tbd tbd tbd gpiod tbd tbd tbd tbd gpioe tbd tbd tbd tbd gpiof tbd tbd tbd tbd crc tbd tbd tbd tbd flash tbd tbd tbd tbd dma1 tbd tbd tbd tbd all enabled tbd tbd tbd tbd i dd (rtc) tbd a i dd (lcd) tbd i dd (adc) (2) tbd i dd (dac) (3) tbd i dd (comp1) tbd i dd (comp2) slow mode tbd fast mode tbd i dd (pvd / bor) (4) tbd i dd (iwdg tbd 1. data based on differential i dd measurement between all peripherals off an one peripheral with clock enabled, in the following conditions: f hclk = 32 mhz, f apb1 = f hclk , f apb2 = f hclk , default prescaler value for each peripheral. the cpu is in sleep mode in bot h cases. no i/o pins toggling. not tested in production. 2. data based on a differential i dd measurement between adc in reset configuration and continuous adc conversion table 21. peripheral current consumption (1) (continued) peripheral typical consumption, v dd = 3.0 v, t a = 25 c unit range 1, v core = 1.8 v vos[1:0] = 01 range 2, v core = 1.5 v vos[1:0] = 10 range 3, v core = 1.2 v vos[1:0] = 11 low power sleep and run electrical characteristics stm32l151xx, stm32l152xx 60/106 doc id 17659 rev 1 6.3.5 external cloc k source characteristics high-speed external user clock generated from an external source the characteristics given in ta b l e 2 2 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 9 . 3. data based on a differential i dd measurement between dac in reset configuration and continuous dac conversion of v dd /2. dac output is left floating. 4. including supply current of internal reference voltage. table 22. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. 1832mhz v hseh osc_in input pin high level voltage 0.7v dd v dd v v hsel osc_in input pin low level voltage v ss 0.3v dd t w(hse) t w(hse) osc_in high or low time (1) tbd ns t r(hse) t f(hse) osc_in rise or fall time (1) tbd c in(hse) osc_in input capacitance (1) 2.6 pf ducy (hse) duty cycle 45 55 % i l osc_in input leakage current v ss v in v dd tbd a stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 61/106 low-speed external user clock generated from an external source the characteristics given in the following table result from tests performed using a low- speed external clock source, and under ambien t temperature and supply voltage conditions summarized in ta b l e 9 . figure 14. high-speed external clock source ac timing diagram table 23. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. 1 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd v dd v v lsel osc32_in input pin low level voltage v ss 0.3v dd t w(lse) t w(lse) osc32_in high or low time (1) tbd ns t r(lse) t f(lse) osc32_in rise or fall time (1) tbd c in(lse) osc32_in input capacitance (1) 0.6 pf ducy (lse) duty cycle tbd tbd % i l osc32_in input leakage current v ss v in v dd tbd a a i / 3 # ? ) . % 8 4 % 2 . ! , 3 4 - , x x # , / # + 3 / 5 2 # % 6 ( 3 % ( t f ( 3 % t 7 ( 3 % ) , 4 ( 3 % t t r ( 3 % t 7 ( 3 % f ( 3 % ? e x t 6 ( 3 % , electrical characteristics stm32l151xx, stm32l152xx 62/106 doc id 17659 rev 1 figure 15. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 1 to 24 mhz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 4 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). table 24. hse 1-24 mhz oscillator characteristics (1)(2) 1. resonator characte ristics given by the crystal/ ceramic resonator manufacturer. 2. based on characterization results, not tested in production. symbol parameter conditions min typ max unit f osc_in oscillator frequency 1 24 mhz r f feedback resistor 200 k c recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) r s = 30 20 pf i 2 hse driving current v dd = 3.3 v, v in =v ss with 30 pf load tbd ma i dd(hse) hse oscillator power consumption c = 20 pf f osc = 16 mhz tbd (startup) tbd (stabilized) (4) ma c = 10 pf f osc = 16 mhz tbd (startup) tbd (stabilized) g m oscillator transconductance startup 3.5 ma /v t su(hse) (5) startup time v dd is stabilized 1 ms a i / 3 # ? ) . % 8 4 % 2 . ! , 3 4 - , x x # , / # + 3 / 5 2 # % 6 , 3 % ( t f , 3 % t 7 , 3 % ) , 4 , 3 % t t r , 3 % t 7 , 3 % f , 3 % ? e x t 6 , 3 % , stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 63/106 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 16 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . refer to the application note an28 67 ?oscillator design guide for st microcontrollers? available fr om the st website www.st.com. figure 16. hse oscillator circuit diagram 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 5 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 3. the relatively low value of the rf resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and t he bias condition change. however, it is recommended to take this point into account if the mcu is used in tough humidity conditions. 4. data based on characterization. not tested in production. 5. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer. table 25. lse oscillator characteristics (f lse = 32.768 khz) (1) symbol parameter conditions min typ max unit f lse low speed external oscillator frequency 32.768 khz r f feedback resistor tbd m c (2) recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) r s = 30 k tbd pf / 3 # ? / 5 4 / 3 # ? ) . f ( 3 % t o c o r e # , # , 2 & 3 4 - 2 e s o n a t o r # o n s u m p t i o n c o n t r o l g m 2 m # m , m # / 2 e s o n a t o r a i electrical characteristics stm32l151xx, stm32l152xx 64/106 doc id 17659 rev 1 note: for c l1 and c l2 , it is recommended to use high-quality ceramic capacitors in the 5 pf to 15 pf range selected to match the requirements of the crystal or resonator (see figure 17 ). c l1 and c l2, are usually the same size. the crystal ma nufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . load capacitance c l has the following formula: c l = c l1 x c l2 / ( c l1 + c l2 ) + c stray where c stray is the pin capacitance and board or trace pcb-related capacitance. typically, it is between 2 pf and 7 pf. caution: to avoid exceeding the maximum value of c l1 and c l2 (15 pf) it is strongly recommended to use a resonator with a load capacitance c l 7 pf. never use a resonator with a load capacitance of 12.5 pf. example: if you choose a resonator with a load capacitance of c l = 6 pf and c stray = 2 pf, then c l1 = c l2 = 8 pf. figure 17. typical application with a 32.768 khz crystal 6.3.6 internal clock source characteristics the parameters given in ta bl e 2 6 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . i lse lse driving current v dd = 3.3 v, v in = v ss tbd a i dd (lse) lse oscillator current consumption v dd = 1.8 v tbd a v dd = 2.4 v tbd v dd = 3.0 v tbd v dd = 3.6v tbd g m oscillator transconductance 5 a/v t su(lse) (4) startup time v dd is stabilized tbd s 1. based on characterization , not tested in production. 2. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 3. the oscillator selection can be optimized in terms of supply current using an hi gh quality resonator with small r s value for example msiv-tin32.768khz. refer to crystal manufacturer for more details; 4. t su(lse) is the startup time measured from the mom ent it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard cr ystal resonator and it can vary significantly with t he crystal manufacturer. table 25. lse oscillator characteristics (f lse = 32.768 khz) (1) (continued) symbol parameter conditions min typ max unit a i / 3 # ? / 5 4 / 3 # ? ) . f , 3 % # , 2 & 3 4 - , x x x k ( z r e s o n a t o r # , 2 e s o n a t o r w i t h i n t e g r a t e d c a p a c i t o r s " i a s c o n t r o l l e d g a i n stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 65/106 high-speed internal (hsi) rc oscillator low-speed internal (lsi) rc oscillator table 26. hsi oscillator characteristics (1) 1. 1.65 v dd 3.6 v, t a = -40 to 105 c unless otherwise specified symbol parameter conditions min typ max unit f hsi frequency v dd = 3.0 v 16 mhz trim hsi user-trimmed resolution -40 c t a 105 c 0.4 tbd % acc hsi accuracy of the hsi oscillator factory- calibrated (2) 2. based on characterization , not tested in production t a = - 40 to 105 c tbd 1tbd% t a = -10 to 85 c tbd 1tbd% t a = 0 to 70 c tbd 1tbd% t a = 25 c tbd 1tbd% t su(hsi) (2) hsi oscillator startup time 3.7 tbd s i dd(hsi) (2) hsi oscillator power consumption 100 tbd a table 27. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = -40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. based on characterization , not tested in production. lsi frequency tbd 38 tbd khz d lsi lsi oscillator frequency drift (3) 0c t a 85c 3. this is a deviation for an individual part, once the in itial frequency has been measured. tdb tdb % t su(lsi) (4) 4. guaranteed by design, not tested in production. lsi oscillator startup time 200 (5) 5. guaranteed by design, not tested in production. s i dd(lsi) (4) lsi oscillator power consumption tbd tbd a electrical characteristics stm32l151xx, stm32l152xx 66/106 doc id 17659 rev 1 multi-speed internal (msi) rc oscillator table 28. msi oscillator characteristics (1) symbol parameter condition min typ max unit f msi frequency after factory calibration, done at v dd = 3.3 v and t a = 25 c msi range 0 tbd 65.5 tbd khz msi range 1 tbd 131 tbd msi range 2 tbd 262 tbd msi range 3 tbd 524 tbd msi range 4 tbd 1.05 tbd mhz msi range 5 tbd 2.1 tbd msi range 6 tbd 4.2 tbd d temp(msi) msi oscillator frequency drift (2) 0c t a 85 c tbd % d volt(msi) msi oscillator frequency drift (3) 1.65 v v dd 3.6 v tbd tbd %/v i dd(msi) (4) msi oscillator power consumption msi range 0 tbd a msi range 1 tbd msi range 2 tbd msi range 3 tbd msi range 4 tbd msi range 5 tbd msi range 6 tbd stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 67/106 t su(msi) msi oscillator startup time msi range 0 tbd s msi range 1 tbd msi range 2 tbd msi range 3 tbd msi range 4 tbd msi range 5 tbd msi range 6, voltage range 1 and 2 tbd msi range 6, voltage range 3 tbd t stab(msi) msi oscillator stabilization time msi range 0 tbd msi range 1 tbd msi range 2 tbd msi range 3 tbd msi range 4 tbd msi range 5 tbd msi range 6, voltage range 1 and 2 tbd msi range 3, voltage range 3 tbd f over(msi) msi oscillator frequency overshoot msi range 0 to range 5 tbd f msi msi range 0 to range 5 voltage range 1 and 2 tbd msi range 0 to range 5 voltage range 3 tbd 1. 1.65 v dd 3.6 v, t a = -40 to 105 c unless otherwise specified. 2. this is a deviation for an individual part, once the in itial frequency has been measured. 3. this is a deviation for an individual part, once the in itial frequency has been measured. 4. based on characterization , not tested in production. table 28. msi oscillator characteristics (1) (continued) symbol parameter condition min typ max unit electrical characteristics stm32l151xx, stm32l152xx 68/106 doc id 17659 rev 1 6.3.7 pll characteristics the parameters given in ta bl e 2 9 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . 6.3.8 memory characteristics the characteristics are given at t a = -40 to 105 c unless otherwise specified. ram memory table 30. ram and hardware registers flash memory table 29. pll characteristics symbol parameter value unit min typ max (1) 1. based on characterization , not tested in production. f pll_in pll input clock (2) 2. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 224mhz pll input clock duty cycle tbd tbd % f pll_out pll multiplier output clock 2 32 mhz t lock pll lock time tbd s jitter cycle-to-cycle jitter tbd ps i dda (pll) current consumption on v dda tbd tbd a i dd (pll) current consumption on v dd tbd tbd symbol parameter conditions min typ max unit vrm data retention mode (1) 1. minimum supply voltage without losing data stored in ram (in stop mode or under reset) or in hardware registers (only in stop mode). guaranteed by characterization, not tested in production. stop mode (or reset) 1.4 v table 31. flash memory characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit v dd operating voltage read / write / erase 1.65 3.6 v t prog programming time for word or half-page erase word/half page tbd ms programmed word/half page tbd i dd supply current during programming / erasing t a = 25 c, v dd = 3.0 v tbd ma t a = 25 c, v dd = 1.8 v tbd ma stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 69/106 6.3.9 emc characteristics susceptibility tests ar e performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in ta b l e 3 3 . they are based on the ems levels and classes defined in application note an1709. table 32. flash memory endurance and data retention symbol parameter conditions value unit min (1) 1. based on characterization not tested in production. typ max n cyc erase / write cycles (program memory) see notes (2) 2. retention guaranteed after cycling is 10 years @ 55*c tbd kcycles erase / write cycles (data memory) see notes (3) 3. retention guaranteed after cycling is 1 year @ 55*c tbd t ret data retention (program memory) after 10 kcycles at t a = 85 c t ret = +55 c tbd ye a r s data retention (data memory) after 10 kcycles at t a = 85 c t ret = +55 c tbd data retention (program memory) after 10 kcycles at t a = 85 c t ret = +85 c tbd table 33. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp100, t a = +25 c, f hclk = 32 mhz conforms to iec 61000-4-2 tbd v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp100, t a = +25 c, f hclk = 32 mhz conforms to iec 61000-4-4 tbd electrical characteristics stm32l151xx, stm32l152xx 70/106 doc id 17659 rev 1 designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o ports). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.10 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its perfor mance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 34. emi characteristics symbol parameter conditions monitored frequency band max vs. voltage range unit 4 mhz 16 mhz 32 mhz s emi peak level v dd = 3.3 v, t a = 25 c, lqfp100 package compliant with iec 61967-2 0.1 to 30 mhz tbd tbd tbd dbv 30 to 130 mhz tbd tbd tbd 130 mhz to 1ghz tbd tbd tbd sae emi level tbd tbd tbd - stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 71/106 static latch-up two complementary static tests are required on six parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.11 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in ta bl e 3 7 are derived from tests performed under the conditions summarized in ta b l e 9 . all i/os are cmos and ttl compliant. table 35. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to jesd22-a114 2tbd v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to jesd22-c101 ii tbd table 36. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a tbd table 37. i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage ttl ports 2.7 v v dd 3.6 v v ss - 0.3 0.8 v v ih standard i/o input high level voltage 2 v dd +0.3 ft (1) i/o input high level voltage 2 5.5v v il input low level voltage cmos ports 1.65 v v dd 3.6 v ?0.3 0.3 v dd v ih standard i/o input high level voltage 0.7 v dd (2) v dd +0.3 ft (3) i/o input high level voltage cmos ports 1.65 v v dd 2.0 v 5.25 cmos ports 2.0 v v dd 3.6 v 5.5 v hys standard i/o schmitt trigger voltage hysteresis (4) 10% v dd (5) i lkg input leakage current (6) v ss v in v dd standard i/os 50 na electrical characteristics stm32l151xx, stm32l152xx 72/106 doc id 17659 rev 1 output driving current the gpios (general purpose input/outputs) can sink or source up to 8 ma, and sink or source up to 20 ma with the non-standard v ol /v oh specifications given in ta b l e 3 8 . in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maxi mum rating specified in section 6.2 : the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see ta bl e 7 ). the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see ta b l e 7 ). output voltage levels unless otherwise specified, the parameters given in ta bl e 3 8 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 9 . all i/os are cmos and ttl compliant. r pu weak pull-up equivalent resistor (7) v in = v ss tbd 45 tbd k r pd weak pull-down equivalent resistor (7) v in = v dd tbd 45 tbd k c io i/o pin capacitance 5 pf 1. ft = 5v tolerant. to sustain a voltage higher than v dd +0.5 the internal pull-up/pull- down resistors must be disabled. 2. 0.7v dd for 5v-tolerant receiver 3. ft = five-volt tolerant. 4. hysteresis voltage between schmitt trigger switching levels. based on characteriza tion, not tested in production. 5. with a minimum of 200 mv. based on characterization, not tested in production. 6. leakage could be higher than max. if negativ e current is injected on adjacent pins. 7. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this mos/nmos contribution to the series resistance is minimum (~10% order) . table 37. i/o static characteristics (continued) symbol parameter conditions min typ max unit stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 73/106 table 38. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always re spect the absolute maximu m rating specified in table 7 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +8 ma 2.7 v < v dd < 3.6 v 0.4 v v oh (2) 2. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 7 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when 8 pins are sourced at same time 2.4 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at same time i io =+ 4ma 1.65 v < v dd < 2.7 v 0.45 v oh (2) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd -0.45 v ol (1)(3) 3. based on characterization data, not tested in production. output low level voltage for an i/o pin when 4 pins are sunk at same time i io = +20 ma 2.7 v < v dd < 3.6 v 1.3 v oh (2)(3) output high level voltage for an i/o pin when 4 pins are sourced at same time v dd -1.3 electrical characteristics stm32l151xx, stm32l152xx 74/106 doc id 17659 rev 1 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 18 and ta bl e 3 9 , respectively. unless otherwise specified, the parameters given in ta bl e 3 9 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 9 . table 39. i/o ac characteristics (1) ospeedrx[1 :0] bit value (1) symbol parameter conditions min max unit 00 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2.7 v to 3.6 v 400 khz c l = 50 pf, v dd = 1.65 v to 2.7 v tbd (3) t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v 625 (3) ns c l = 50 pf, v dd = 1.65 v to 2.7 v tbd (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2.7 v to 3.6 v 2 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v tbd (3) t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v 125 (3) ns c l = 50 pf, v dd = 1.65 v to 2.7 v tbd (3) 10 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2.7 v to 3.6 v 10 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v tbd (3) t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v 25 (3) ns c l = 50 pf, v dd = 1.65 v to 2.7 v tbd (3) 11 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2.7 v to 3.6 v 50 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v tbd (3) t f(io)out t r(io)out output rise and fall time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) ns c l = 50 pf, v dd = 1.65 v to 2.7 v tbd (3) -t extipw pulse width of external signals detected by the exti controller tbd 1. the i/o speed is configured using the modex[1:0] bits. refer to the stm32l15xxx reference manual for a description of gpio port configuration register. 2. the maximum frequency is defined in figure 18 . 3. guaranteed by design, not tested in production. stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 75/106 figure 18. i/o ac characteristics definition 6.3.12 nrst pin characteristics the nrst pin input driver uses cmos techno logy. it is connected to a permanent pull-up resistor, r pu (see ta bl e 3 7 ). unless otherwise specified, the parameters given in ta bl e 4 0 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 9 . ai14131 10% 90% 50% t r(io)out external output on 50pf maximum frequency is achieved if (t r + t f ) 2/3)t and if the duty cycle is (45-55%) 10 % 50% 90% when loaded by 50 pf t t r(io)out table 40. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) 1. guaranteed by design, not tested in production. nrst input low level voltage v ss 0.8 v v ih(nrst) (1) nrst input high level voltage 1.4 v dd v ol(nrst) (1) nrst output low level voltage i ol = 2 ma 2.7 v < v dd < 3.6 v 0.4 i ol = 1.5 ma 1.65 v < v dd < 2.7 v v hys(nrst) nrst schmitt trigger voltage hysteresis 10%v dd (2) 2. 200 mv minimum value mv r pu weak pull-up equivalent resistor (3) 3. the pull-up is designed with a true resistance in seri es with a switchable pmos. this pmos contribution to the series resistance is around 10%. v in = v ss tbd 45 tbd k v f(nrst) (1) nrst input filtered pulse 50 ns v nf(nrst) (1) nrst input not filtered pulse 350 ns electrical characteristics stm32l151xx, stm32l152xx 76/106 doc id 17659 rev 1 figure 19. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 40 . otherwise the reset will not be taken into account by the device. 6.3.13 tim time r characteristics the parameters given in the following table are guaranteed by design. refer to section 6.3.11: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). a i 3 4 - , x x x 2 0 5 . 2 3 4 6 $ $ & i l t e r ) n t e r n a l r e s e t ? & % x t e r n a l r e s e t c i r c u i t table 41. timx (1) characteristics 1. timx is used as a general term to refer to the tim1, tim2, tim3 and tim4 timers. symbol parameter conditions min max unit t res(tim) timer resolution time 1 t timxclk f timxclk = 32 mhz 31.25 ns f ext timer external clock frequency on ch1 to ch4 0 f timxclk /2 mhz f timxclk = 32 mhz 0 36 mhz res tim timer resolution 16 bit t counter 16-bit counter clock period when internal clock is selected (timer?s prescaler disabled) 1 65536 t timxclk f timxclk = 32 mhz 0.0312 2048 s t max_count maximum possible count 65536 65536 t timxclk f timxclk = 32 mhz 134.2 s stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 77/106 6.3.14 communications interfaces i 2 c interface characteristics unless otherwise specified, the parameters given in ta bl e 4 2 are derived from tests performed under ambient temperature, f pclk1 frequency and v dd supply voltage conditions summarized in ta b l e 9 . the line i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: sda and scl are not ?true? open-drain i/o pins. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in ta b l e 4 2 . refer also to section 6.3.11: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 42. i 2 c characteristics symbol parameter standard mode i 2 c (1) 1. guaranteed by design, not tested in production. fast mode i 2 c (1) (2) 2. f pclk1 must be higher than 2 mhz to achieve standard mode i 2 c frequencies. it must be higher than 4 mhz to achieve fast mode i2c frequencies. it must be a mu ltiple of 10 mhz to reach the 400 khz maximum i2c fast mode clock. unit min max min max t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. 0 (4) 4. the device must internally provide a hold time of at least 300 ns for th e sda signal in order to bridge the undefined region of the falling edge of scl. 900 (3) t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf electrical characteristics stm32l151xx, stm32l152xx 78/106 doc id 17659 rev 1 figure 20. i 2 c bus ac waveforms and measurement circuit 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . table 43. scl frequency (f pclk1 = 36 mhz, v dd = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed. 2. for speeds around 200 khz, the tole rance on the achieved speed is of 5%. for other speed ranges, the tolerance on the achieved speed is 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k 400 0x801e 300 0x8028 200 0x803c 100 0x00b4 50 0x0168 20 0x0384 a i 3 4 ! 2 4 3 $ ! ? k ? ) # b u s k ? ? 6 $ $ 6 $ $ 3 4 - , x x x 3 $ ! 3 # , t f 3 $ ! t r 3 $ ! 3 # , t h 3 4 ! t w 3 # + ( t w 3 # + , t s u 3 $ ! t r 3 # + t f 3 # + t h 3 $ ! 3 4 ! 2 4 2 % 0 % ! 4 % $ 3 4 ! 2 4 t s u 3 4 ! t s u 3 4 / 3 4 / 0 t s u 3 4 ! 3 4 / stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 79/106 spi characteristics unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta bl e 9 . refer to section 6.3.11: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). table 44. spi characteristics (1) 1. remapped spi1 characteristics to be determined. symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode 16 mhz slave mode 16 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf tbd ns ducy(sck) spi slave input clock duty cycle slave mode 30 70 % t su(nss) (2) 2. based on characterization , not tested in production. nss setup time slave mode 4t pclk ns t h(nss) (2) nss hold time slave mode 2t pclk t w(sckh) (2) t w(sckl) (2) sck high and low time master mode, f pclk = 16 mhz, presc = 4 tbd tbd t su(mi) (2) t su(si) (2) data input setup time master mode 5 slave mode 5 t h(mi) (2) data input hold time master mode 5 t h(si) (2) slave mode 4 t a(so) (2)(3) 3. min time is for the minimum time to drive the output and max time is for the maximum time to validate the data. data output access time slave mode, f pclk = 20 mhz 0 3t pclk t dis(so) (2)(4) 4. min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in hi-z. data output disable time slave mode tbd tbd t v(so) (2)(1) data output valid time slave mode (after enable edge) tbd t v(mo) (2)(1) data output valid time master mode (after enable edge) tbd t h(so) (2) data output hold time slave mode (after enable edge) tbd t h(mo) (2) master mode (after enable edge) tbd electrical characteristics stm32l151xx, stm32l152xx 80/106 doc id 17659 rev 1 figure 21. spi timing diagram - slave mode and cpha = 0 figure 22. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 81/106 figure 23. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . usb characteristics the usb interface is usb-if certified (full speed). table 45. usb startup time symbol parameter max unit t startup (1) 1. guaranteed by design, not tested in production. usb transceiver startup time 1 s ai14136 sck input cpha= 0 mosi output miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo) electrical characteristics stm32l151xx, stm32l152xx 82/106 doc id 17659 rev 1 figure 24. usb timings: definition of data signal rise and fall time table 46. usb dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input levels v dd usb operating voltage (2) 2. to be compliant with the usb 2.0 fu ll-speed electrical specification, the usbdp (d+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 v voltage range. 3.0 (3) 3. the stm32l15xxx usb functionality is ensured down to 2.7 v but not the full usb electrical c haracteristics which are degraded in the 2.7-to-3.0 v v dd voltage range. 3.6 v v di (4) 4. guaranteed by characterizati on, not tested in production. differential input sensitivity i(usbdp, usbdm) 0.2 v v cm (4) differential common mode range includes v di range 0.8 2.5 v se (4) single ended receiver threshold 1.3 2.0 output levels v ol static output level low r l of 1.5 k to 3.6 v (5) 5. r l is the load connected on the usb drivers. 0.3 v v oh static output level high r l of 15 k to v ss (5) 2.8 3.6 table 47. usb: full-speed electrical characteristics driver characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter con ditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapt er 7 (version 2.0). c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal crossover voltage 1.3 2.0 v ai14137 t f differen tial data l ines v ss v cr s t r crossover points stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 83/106 6.3.15 12-bit adc characteristics unless otherwise specified, the parameters given in ta bl e 4 8 are derived from tests performed under ambient temperature, f pclk2 frequency and v dda supply voltage conditions summarized in ta bl e 9 . table 48. adc characteristics symbol parameter conditions min typ max unit v dda power supply 1.8 3.6 v v ref+ positive reference voltage 2.4 v v dda 3.6 v 2.4 v dda 1.8 v v dda 2.4 v v dda v ref- negative reference voltage v ssa i vdda current on the v dda input pin 1000 a i vref current on the v ref input pin 400 (1) tbd v ain conversion voltage range (2) 0 (3) v ref+ v f adc adc clock frequency 2.4 v v dda 3.6v 0.320 16 mhz 1.8 v v dda 2.4v voltage range 1 & 2 0.320 8 1.8 v v dda 2.4v voltage range 3 0.320 4 f s (4) sampling rate direct channels 0.02 1 msps multiplexed channels 0.02 tbd t s sampling time f adc = 16 mhz 0.107 17.1 s 43841/f adc t conv total conversion time (including sampling time) f adc = 16 mhz 1 24.75 s 4 to 384 (sampling phase) +12 (successive approximation) 1/f adc r adc sampling switch resistance direct channels tbd k multiplexed channels tbd c adc internal sample and hold capacitor direct channels tbd pf multiplexed channels tbd f trig external trigger frequency f adc = 16 mhz tbd khz tbd 1/f adc r ain (5) external input impedance tbd k t lat injection trigger conversion latency f adc = 16 mhz tbd s tbd 1/f adc t latr regular trigger conversion latency f adc = 16 mhz tbd s tbd 1/f adc t stab power-up time 3.5 s electrical characteristics stm32l151xx, stm32l152xx 84/106 doc id 17659 rev 1 1. based on characterization results, not tested in production. 2. v ref+ can be internally connected to v dda and v ref- can be internally connected to v ssa , depending on the package. refer to section 4: pin description for further details. 3. v ssa or v ref- must be tied to ground. 4. guaranteed by design, not tested in production. 5. for 1 msps, maximum rext is 0.5 k . table 49. adc accuracy - limited test conditions (1)(2) 1. adc dc accuracy values are m easured after internal calibration. 2. adc accuracy vs. negative injection current: injecti ng negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the ac curacy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current wi thin the limits specified for i inj(pin) and i inj(pin) in section 6.3.11 does not affect the adc accuracy. symbol parameter test conditions typ max (3) 3. based on characterization , not tested in production. unit et total unadjusted error tbd tbd lsb eo offset error tbd tbd eg gain error tbd tbd ed differential linearity error tbd tbd el integral linearity error tbd tbd stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 85/106 figure 25. adc accura cy characteristics table 50. adc accuracy (1)(2) 1. better performance could be achieved in restricted v dd , frequency, v ref and temperature ranges. 2. adc accuracy vs. negative injection current: in jecting negative current on any of the standard (non- robust) analog input pins should be av oided as this significantly reduce s the accuracy of the conversion being performed on another analog input. it is recommend ed to add a schottky diode (pin to ground) to standard analog pins which may pot entially inject negative current. any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 6.3.11 does not affect the adc accuracy. symbol parameter test conditions typ max (3) 3. based on characterization , not tested in production. unit et total unadjusted error f pclk2 = 56 mhz, f adc = 14 mhz, r ain < 10 k , v dda = 2.4 v to 3.6 v measurements made after adc calibration tbd tbd lsb eo offset error tbd tbd eg gain error tbd tbd ed differential linearity error tbd tbd el integral linearity error tbd tbd enob effective number of bits tbd tbd bits sinad signal-to-noise and distortion ratio tbd tbd db snr signal-to-noise ratio tbd tbd thd total harmonic distortion tbd tbd e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa ai14395b v ref+ 4096 (or depending on package)] v dda 4096 [1lsb ideal = electrical characteristics stm32l151xx, stm32l152xx 86/106 doc id 17659 rev 1 figure 26. typical connection diagram using the adc 1. refer to ta b l e 4 8 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 27 or figure 28 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed as close as possible to the chip. figure 27. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref? inputs are available only on 100-pin packages. a i 3 4 - , x x x 6 $ $ ! ) . x ) , ? ? ! 6 6 4 2 ! ) . # p a r a s i t i c 6 ! ) . 6 6 4 2 ! $ # b i t c o n v e r t e r # ! $ # 3 a m p l e a n d h o l d ! $ # c o n v e r t e r 6 2 % & s e e n o t e 3 4 - , x x x 6 $ $ ! 6 3 3 ! 6 2 % & n s e e n o t e ? & n & ? & n & a i stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 87/106 figure 28. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref? inputs are available only on 100-pin packages. 6 2 % & 6 $ $ ! 3 4 - , x x x ? & n & 6 2 % & n 6 3 3 ! a i 3 e e n o t e 3 e e n o t e electrical characteristics stm32l151xx, stm32l152xx 88/106 doc id 17659 rev 1 6.3.16 dac elect rical specifications table 51. dac characteristics symbol parameter conditions min typ max unit v dda analog supply voltage 1.8 3.6 v v ref+ reference supply voltage v ref+ must always be below v dda 1.8 3.6 v ssa ground 0 0 i ddvref+ current consumption on v ref+ supply 210 a i dda current consumption on v dda supply no load, middle code (0x800) 370 tbd no load, worst code (0xf1c) with v ref+ = 3.6 v 500 tbd r l (1) resistive load dac output buffer on 5k c l (1) capacitive load 50 pf r o output impedance dac output buffer off tbd k v dac_out voltage on dac_out output dac output buffer on 0.2 v dda ? 0.2 v dac output buffer off 0.5 v ref+ ? 1lsb mv dnl differential non linearity c l 50 pf, r l 5 k dac output buffer on 1 tbd lsb c l 50 pf dac output buffer off tbd tbd inl integral non linearity c l 50 pf, r l 5 k dac output buffer on 2 tbd c l 50 pf dac output buffer off tbd tbd offset offset error (difference between the value measured at code (0x800) and the ideal value = v ref+ /2) c l 50 pf, r l 5 k dac output buffer on 10 mv c l 50 pf dac output buffer off tbd tbd gain error gain error c l 50 pf, r l 5 k dac output buffer on 0.5 tbd % c l 50 pf dac output buffer off tbd tbd stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 89/106 figure 29. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. 6.3.17 temperature sen sor characteristics tue total unadjusted error c l 50 pf, r l 5 k dac output buffer on tbd tbd lsb c l 50 pf dac output buffer off tbd tbd t settling settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes till dac_out reaches final value 1lsb c l 50 pf, r l 5 k 7tbds update rate max frequency for a correct dac_out change (95% of final value) with 1 lsb variation in the input code c l 50 pf, r l 5 k 1 msps t wakeup wakeup time from off state (setting the enx bit in the dac control register) c l 50 pf, r l 5 k 9tbds psrr+ v dda supply rejection ratio (static dc measurement) c l 50 pf, r l 5 k -60 -35 db 1. connected between dac_out and v ssa . table 51. dac characteristics (continued) symbol parameter conditions min typ max unit r load c load b u ffered/non- bu ffered dac dacx_out b u ffer(1) 12- b it digit a l to a n a log converter a i17157 table 52. ts characteristics symbol parameter min typ max unit t l (1) v sense linearity with temperature 1tbdc avg_slope (1) average slope tbd 1.62 tbd mv/c v 90 (1) voltage at 90c 5c (2) tbd 0.597 tbd v i dda (temp) current consumption 3.4 6 a electrical characteristics stm32l151xx, stm32l152xx 90/106 doc id 17659 rev 1 6.3.18 comparator t start (3) startup time 10 s t s_temp (4)(3) adc sampling time when reading the temperature 510 1. guaranteed by characterizati on, not tested in production. 2. measured at v dd = 3 v 10 mv. v90 adc conversion result is stored in the ts_factory_conv_v90 byte. 3. guaranteed by design, not tested in production. 4. shortest sampling time can be determined in the application by multiple iterations. table 52. ts characteristics (continued) symbol parameter min typ max unit table 53. comparator 1 characteristics symbol parameter min typ max (1) 1. based on characterization , not tested in production. unit v dda analog supply voltage 1.65 3.6 v r 400k r 400k value 400 k r 10k r 10k value 10 v in comparator 1 input voltage range 0 v dda - tbd v v refint internal reference voltage 1.225 t start comparator startup time 7 s td propagation delay (2) 2. the delay is characterized for 100 mv input step wi th 10 mv overdrive on the inverting input, the non- inverting input set to the reference. 3 voffset comparator offset error 3 mv i comp1 current consumption (3) 3. comparator consumption only. inte rnal reference voltage not included. 160 tbd na table 54. comparator 2 characteristics symbol parameter conditions min typ max (1) unit v dda analog supply voltage 1.65 3.6 v v in comparator 2 input voltage range 0 v dda v t start comparator startup time fast mode tbd s slow mode tbd t d slow propagation delay (2) in slow mode 1.65 v v dda 2.7 v tbd tbd 2.7 v v dda 3.6 v tbd tbd t d fast propagation delay (3) in fast mode 1.65 v v dda 2.7 v tbd tbd 2.7 v v dda 3.6 v tbd tbd stm32l151xx, stm32l152xx electrical characteristics doc id 17659 rev 1 91/106 6.3.19 lcd control ler (stm32l152xx only) the stm8l152xx embeds a built-in step-up converter to provide a constant lcd reference voltage independently from the v dd voltage. an external capacitor c ext must be connected to the v lcd pin to decouple this converter. v offset comparator offset error tbd mv i comp2 current consumption (4) fast mode tbd tbd a slow mode tbd tbd 1. based on characterization , not tested in production. 2. the delay is characterized for 100 mv input step wi th 10 mv overdrive on the inverting input, the non- inverting input set to the reference. 3. the delay is characterized for 100 mv input step wi th 10 mv overdrive on the inverting input, the non- inverting input set to the reference. 4. comparator consumption only. inte rnal reference voltage not included. table 54. comparator 2 characteristics (continued) symbol parameter conditions min typ max (1) unit table 55. lcd controller characteristics symbol parameter min typ max unit v lcd lcd external voltage 3.6 v v lcd0 lcd internal reference voltage 0 2.6 v lcd1 lcd internal reference voltage 1 2.7 v lcd2 lcd internal reference voltage 2 0 2.8 v lcd3 lcd internal reference voltage 3 2.9 v lcd4 lcd internal reference voltage 4 3 v lcd5 lcd internal reference voltage 5 3.1 v lcd6 lcd internal reference voltage 6 3.2 v lcd7 lcd internal reference voltage 7 3.3 c ext v lcd external capacitance 0.1 2 f i lcd (1) supply current at v dd = 1.8 v tbd a supply current at v dd = 1.8 v tbd r h low drive resistive network tbd m r l high drive resistive network tbd k v 44 segment/common highest level voltage v lcd v v 34 segment/common 3/4 level voltage 3/4 v lcd v v 23 segment/common highest level voltage 2/3 v lcd v 12 segment/common highest level voltage 1/2 v lcd v 13 segment/common highest level voltage 1/3 v lcd electrical characteristics stm32l151xx, stm32l152xx 92/106 doc id 17659 rev 1 v 14 segment/common highest level voltage 1/4 v lcd v v 0 segment/common lowest level voltage 0 v 1. lcd enabled with 3 v internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no lcd connected table 55. lcd controller characteristics (continued) symbol parameter min typ max unit stm32l151xx, stm32l152xx package characteristics doc id 17659 rev 1 93/106 7 package characteristics 7.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. package characteristics stm32l151xx, stm32l152xx 94/106 doc id 17659 rev 1 figure 30. vfqfpn48 7 x 7 mm, 0.5 mm pitch, package outline (1) figure 31. recommended footprint (dimensions in mm) (1) 1. drawing is not to scale. seating plane a3 a1 a2 a d e e e2 b e l l d2 b v0_me c 12 13 24 25 36 37 1 48 7.30 7.30 0.20 0.30 0.55 0.50 5.80 6.20 6.20 5.60 5.60 5.80 0.75 ai15697 48 1 12 13 24 25 36 37 table 56. vfqfpn48 ? very thin fine pitch quad flat pack nolead 7 7 mm, 0.5 mm pitch package mechanical data symbol millimeters inches (1) typ min max typ min max a 0.900 0.800 1.000 0.0354 0.0315 0.0394 a1 0.020 0.050 0.0008 0.0020 a2 0.650 1.000 0.0256 0.0394 a3 0.250 0.0098 b 0.230 0.180 0.300 0.0091 0.0071 0.0118 d 7.000 6.850 7.150 0.2756 0.2697 0.2815 d2 4.700 2.250 5.250 0.1850 0.0886 0.2067 e 7.000 6.850 7.150 0.2756 0.2697 0.2815 e2 4.700 2.250 5.250 0.1850 0.0886 0.2067 e 0.500 0.450 0.550 0.0197 0.0177 0.0217 l 0.400 0.300 0.500 0.0157 0.0118 0.0197 ddd 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. stm32l151xx, stm32l152xx package characteristics doc id 17659 rev 1 95/106 figure 32. recommended pcb design rules for pads (0.5 mm pitch bga) 1. non solder mask defined (nsmd) pads are recommended 2. 4 to 6 mils solder paste screen printing process pitch 0.5 mm d pad 0.27 mm dsm 0.35 mm typ (depends on the soldermask registration tolerance) solder paste 0.27 mm aperture diameter dpad dsm ai15495 package characteristics stm32l151xx, stm32l152xx 96/106 doc id 17659 rev 1 figure 33. tfbga64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline 1. drawing is not to scale. table 57. tfbga64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.200 0.0472 a1 0.150 0.0059 a2 0.785 0.0309 a3 0.200 0.0079 a4 0.600 0.0236 b 0.250 0.300 0.350 0.0098 0.0118 0.0138 d 4.850 5.000 5.150 0.1909 0.1969 0.2028 d1 3.500 0.1378 e 4.850 5.000 5.150 0.1909 0.1969 0.2028 e1 3.500 0.1378 e 0.500 0.0197 f 0.750 0.0295 ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.050 0.0020 a 3 a4 a2 a1 a s e a ting pl a ne b a d d1 e f f e1 e e h g f e d c b a 12 3 4567 8 a1 ba ll p a d corner ? b (64 ba ll s ) bottom view c me_r 8 stm32l151xx, stm32l152xx package characteristics doc id 17659 rev 1 97/106 figure 34. ufbga100 - ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package outline 1. drawing is not to scale. a1 ba ll p a d corner top view s ide view bottom view a1 ba ll p a d corner e d e1 e fe d1 fd 0.50 0.10 a1 a a2 1.75 1.75 0.10 z x y a0c2_me b table 58. ufbga100 - ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.46 0.53 0.6 0.0181 0.0209 0.0236 a1 0.06 0.08 0.1 0.0024 0.0031 0.0039 a2 0.4 0.45 0.5 0.0157 0.0177 0.0197 b 0.2 0.25 0.3 0.0079 0.0098 0.0118 d 7 0.2756 d1 5.5 0.2165 e 7 0.2756 e1 5.5 0.2165 e 0.5 0.0197 fd 0.75 0.0295 fe 0.75 0.0295 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32l151xx, stm32l152xx 98/106 doc id 17659 rev 1 figure 35. lqfp100, 14 x 14 mm, 100-pin low-profile quad flat package outline (1) figure 36. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. d d1 d3 75 51 50 76 100 26 125 e3 e1 e e b pin 1 identification seating plane gage plane c a a2 a1 c ccc 0.25 mm 0.10 inch l l1 k c 1l_me 75 51 50 76 0.5 0.3 16.7 14.3 100 26 12.3 25 1.2 16.7 1 ai14906 table 59. lqpf100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.6 0.063 a1 0.05 0.15 0.002 0.0059 a2 1.35 1.4 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.2 0.0035 0.0079 d 15.8 16 16.2 0.622 0.6299 0.6378 d1 13.8 14 14.2 0.5433 0.5512 0.5591 d3 12 0.4724 e 15.8 16 16.2 0.622 0.6299 0.6378 e1 13.8 14 14.2 0.5433 0.5512 0.5591 e3 12 0.4724 e 0.5 0.0197 l 0.45 0.6 0.75 0.0177 0.0236 0.0295 l1 1 0.0394 k 0.0 3.5 7.0 0.0 3.5 7.0 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. stm32l151xx, stm32l152xx package characteristics doc id 17659 rev 1 99/106 figure 37. lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package outline (1) figure 38. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. a a2 a1 c l1 l e e1 d d1 e b ai14398b 48 32 49 64 17 116 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 table 60. lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 12.00 0.4724 d1 10.00 0.3937 e 12.00 0.4724 e1 10.00 0.3937 e 0.50 0.0197 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 n number of pins 64 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32l151xx, stm32l152xx 100/106 doc id 17659 rev 1 figure 39. lqfp48, 7 x 7 mm, 48-pin low-profile quad flat package outline (1) figure 40. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. d d1 d3 a1 l1 l k c b ccc c a1 a2 a c seating plane 0.25 mm gage plane e3 e1 e 12 13 24 25 48 1 36 37 pin 1 identification 5b_me 9.70 5.80 7.30 12 24 0.20 7.30 1 37 36 1.20 5.80 9.70 0.30 25 1.20 0.50 ai14911b 13 48 table 61. lqfp48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data symbol millimeters inches (1) typ min max typ min max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.400 1.350 1.450 0.0551 0.0531 0.0571 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 c 0.090 0.200 0.0035 0.0079 d 9.000 8.800 9.200 0.3543 0.3465 0.3622 d1 7.000 6.800 7.200 0.2756 0.2677 0.2835 d3 5.500 0.2165 e 9.000 8.800 9.200 0.3543 0.3465 0.3622 e1 7.000 6.800 7.200 0.2756 0.2677 0.2835 e3 5.500 0.2165 e 0.500 0.0197 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 k 3.50 73.50 7 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. stm32l151xx, stm32l152xx package characteristics doc id 17659 rev 1 101/106 7.2 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max ja ) where: t a max is the maximum ambient temperature in c, ja is the package junction-to-ambient thermal resistance, in c/w, p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum powe r dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). ava ilable from www.jedec.org. table 62. thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient bga100 - 7 x 7 mm tbd c/w thermal resistance junction-ambient lqfp100 - 14 x 14 mm / 0.5 mm pitch 46 thermal resistance junction-ambient lqfp64 - 10 x 10 mm / 0.5 mm pitch 45 thermal resistance junction-ambient lqfp48 - 7 x 7 mm / 0.5 mm pitch 55 thermal resistance junction-ambient vfqfpn48 - 7 x 7 mm / 0.5 mm pitch 16 package characteristics stm32l151xx, stm32l152xx 102/106 doc id 17659 rev 1 7.2.2 selecting the pro duct temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in table 63: ordering information scheme . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. as applications do not commonly use the stm32 l15xxx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. the following examples show how to calculate the temperature range needed for a given application. example 1: high-performance application assuming the following application conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw: p dmax = 175 + 272 = 447 mw thus: p dmax = 447 mw using the values obtained in ta b l e 6 2 t jmax is calculated as follows: ? for lqfp100, 46 c/w t jmax = 82 c + (46 c/w 447 mw) = 82 c + 20.6 c = 102.6 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suffix 6 (see table 63: ordering information scheme ). example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following application conditions: maximum ambient temperature t amax = 115 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 20 8 ma 0.4 v = 64 mw this gives: p intmax = 70 mw and p iomax = 64 mw: p dmax = 70 + 64 = 134 mw thus: p dmax = 134 mw stm32l151xx, stm32l152xx package characteristics doc id 17659 rev 1 103/106 using the values obtained in ta b l e 6 2 t jmax is calculated as follows: ? for lqfp100, 46 c/w t jmax = 115 c + (46 c/w 134 mw) = 115 c + 6.2 c = 121.2 c this is within the range of the suffix 7 version parts (?40 < t j < 125 c). in this case, parts must be ordered at least with the temperature range suffix 7 (see table 63: ordering information scheme ). figure 41. lqfp100 p d max vs. t a 0 100 200 300 400 500 600 700 65 75 85 95 105 115 125 135 t a (c) p d (mw) suffix 6 suffix 7 ordering information scheme stm32l151xx, stm32l152xx 104/106 doc id 17659 rev 1 8 ordering information scheme for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 63. ordering information scheme example: stm32 l 151 c 8 t 6 d xxx device family stm32 = arm-based 32-bit microcontroller product type l = low power device subfamily 151: devices without lcd 152: devices with lcd pin count c = 48 pins r = 64 pins v = 100 pins flash memory size 8 = 64 kbytes of flash memory b = 128 kbytes of flash memory package h = bga t = lqfp u = vfqfpn temperature range 6 = industrial temperature range, ?40 to 85 c options no character = v dd range: 1.8 to 3.6 v and bor enabled d = v dd range: 1.65 to 3.6 v and bor disabled packing tr = tape and reel no character = tray or tube stm32l151xx, stm32l152xx revision history doc id 17659 rev 1 105/106 9 revision history table 64. document revision history date revision changes 02-jul-2010 1 initial release. stm32l151xx, stm32l152xx 106/106 doc id 17659 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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